Junction field effect transistor, and method of manufacture thereof
View Patent ↗A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.
1. A junction field effect transistor comprising:
a channel;
a gate; and
a drain and a source, wherein the drain and the source are in controllable current flow communication by way of the channel,
wherein a depth di of current flow is represented by:
di
=
Wtg
+
(
2
Wch
3
)
where Wtg represents a depth of the top gate, and
Wch represents a width of the channel between the top gate and the back gate.
2. A junction field effect transistor as claimed in claim 1 , in which a depth of the drain exceeds 0.5 μm.
3. A junction field effect transistor as claimed in claim 1 , in which a depth W 2 ch of the channel, is related to a distance Ld between the gate and the source by
W
2
ch
=
Ld
β
where β is a coefficient greater than 2.5.
4. A junction field effect transistor as claimed in claim 3 , where β is in the range 3≦β≦4.
5. A junction field effect transistor as claimed in claim 1 , where a width Wch of the channel in a first channel region beneath the gate is related to a channel depth W 2 ch in a region between the gate and the drain by
Wch =α( W 2 ch−Wtg )
where Wtg is a depth of the gate, and a is a coefficient between 0.5 and 1.
6. A junction field effect transistor as claimed in claim 1 , in which, for a given maximum design voltage, the distance Ld between the gate and the source is at least 1.3 times greater than a distance for setting a horizontal electric field between the gate and the source below a threshold strength of substantially 3×10 5 Vcm −1 .
7. A junction field effect transistor as claimed in claim 1 , in which, in use and at a maximum design operating voltage, the ratio of gate current to drain current is less than 10 −7 .
8. An integrated circuit comprising at least one transistor as claimed in claim 1 .
9. A junction field effect transistor as claimed in claim 1 , wherein a first channel dimension is selected such that the majority of current flow in the channel occurs in a region where electric field strength is below a threshold at which impact ionization is negligible.
10. A junction field effect transistor comprising:
a channel;
a gate; and
a drain and a source, wherein the drain and source are in controllable current flow communication by way of the channel,
wherein the gate is a top gate and the junction field effect transistor further comprises a back gate, and wherein a separation Ld between the top gate and the drain is related to a depth of the channel between the top gate and the drain by
W
2
ch
=
Ld
β
where W 2 ch is the channel depth (distance to the top of the back gate), and
β is a coefficient greater than 2.5.
11. A junction field effect transistor as claimed in claim 10 , where a width Wch of the channel in a first channel region beneath the gate is related to a channel depth W 2 ch in a region between the gate and the drain by
Wch =α( W 2 ch−Wtg )
where Wtg is a depth of the gate, and α is a coefficient between 0.5 and 1.
12. A junction field effect transistor as claimed in claim 10 , in which the drain has a depth of at least 0.5 μm.
13. A junction field effect transistor as claimed in claim 10 , in which, for a given maximum design voltage, the distance Ld between the gate and the source is at least 1.3 times greater than a distance for setting a horizontal electric field between the gate and the source below a threshold strength of substantially 3×10 5 Vcm −1 .
14. A junction field effect transistor as claimed in claim 10 , in which, in use and at a maximum design operating voltage, the ratio of gate current to drain current is less than 10 −7 .
15. An integrated circuit comprising at least one transistor as claimed in claim 10 .
16. A junction field effect transistor as claimed in claim 10 , wherein a first channel dimension is selected such that the majority of current flow in the channel occurs in a region where electric field strength is below a threshold at which impact ionization is negligible.
17. A junction field effect transistor as claimed in claim 10 , in which the drain has a depth greater than a depth of the top gate Wtg.
18. A junction field effect transistor as claimed in claim 10 , where β is in the range 3≦β≦4.
19. A junction field effect transistor as claimed in claim 10 , in which Ld has a dimension such that at a maximum design operating voltage Ld/β is less than a semiconductor breakdown threshold.
20. A junction field effect transistor as claimed in claim 10 , in which Ld is selected such that a maximum design operating voltage Ld/β is less than 3×10 5 Vcm −1 .