IP Library Granted Patent US 8,885,786
Granted Patent B2
US 8,885,786 · App. 14/057,080 · Granted Nov 11, 2014

Fine phase estimation for highly spectrally efficient communications

Inventor: Amir Eliaz (Moshav Ben Shemen, IL)
Assignee: MagnaCom Ltd.
H04L25/03038H04L27/01H04B1/709G06F11/10H04L27/02H04L25/03949H04L27/04H04L27/36H04L25/03057H04L25/03318H04L25/03305H04L25/03834H04L7/0087H04L23/02H04L25/03178H04L1/206H04L25/03337H04L25/03006H04L27/00H04B1/10H04B1/16
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Quick Facts
Patent No.
US 8,885,786
App. No.
14/057,080
Granted
Nov 11, 2014
Kind
B2
Abstract

A receiver may process a received signal to generate a processed received signal. The receiver may generate, during a sequence estimation process, an estimate of a phase error of the processed received signal. The receiver may generate an estimate of a value of a transmitted symbol corresponding to the received signal based on the estimated phase error. The generation of the estimate of the phase error may comprise generation of one or more phase candidate vectors. The generation of the estimate may comprise calculation of a metric based on the one or more phase candidate vectors. The calculation of the metric may comprise phase shifting the processed received signal based on the estimated phase error resulting in a phase-corrected received signal. The calculation of the metric may comprise calculating a Euclidean distance based on the phase-corrected received signal and one or more symbol candidate vectors.

Claims (45)

1. A method comprising:

processing, in a receiver, a received inter-symbol correlated (ISC) signal, said processing resulting in a processed received ISC signal, wherein said processing comprises coarsely adjusting a phase of said received ISC signal based on an output of a carrier recovery circuit of said receiver;

generating, via a sequence estimation process performed by said receiver, an estimate of a phase error of said processed received ISC signal, wherein said sequence estimation process concurrently operates on a plurality of symbols of said processed received ISC signal; and

generating an estimate of a value of a transmitted symbol corresponding to said received ISC signal based on said estimate of said phase error.

2. The method of claim 1 , wherein said sequence estimation process comprises generating one or more phase candidate vectors, each of said one or more phase candidate vectors comprising a plurality of phase values.

3. The method of claim 1 , wherein the received ISC signal is a partial response signal generated via a partial response filter.

4. The method of claim 1 , wherein said estimate of said phase error of said processed received ISC signal is an estimate of a residual phase error remaining after said coarsely adjusting.

5. The method of claim 2 , comprising selecting a best one of said one or more phase candidate vectors as said estimate of said phase error of said processed received ISC signal.

6. A system comprising:

a carrier recovery circuit;

a signal processing circuit operable to process a received inter-symbol correlated (ISC) signal, said processing resulting in a processed received ISC signal, wherein said processing of said received ISC signal comprises coarsely adjusting a phase of said received ISC signal based on an output of said carrier recovery circuit; and

a sequence estimation circuit operable to concurrently operate on a plurality of symbols of said processed received ISC signal to:

generate an estimate of a phase error of said processed received ISC signal; and

generate an estimate of a value of a transmitted symbol corresponding to said received ISC signal based on said estimate of said phase error.

7. The system of claim 6 , wherein said sequence estimation circuit is operable to generate one or more phase candidate vectors, each of said one or more phase candidate vectors comprising a plurality of phase values.

8. The system of claim 6 , wherein the received ISC signal is a partial response signal generated via a partial response filter.

9. The system of claim 6 , wherein said estimate of said phase error of said processed received ISC signal is an estimate of a residual phase error remaining after said coarsely adjusting.

10. The system of claim 7 , wherein said sequence estimation circuit is operable to select a best one of said one or more phase candidate vectors as said estimate of said phase error of said processed received ISC signal.

11. A receiver comprising:

a phase adjustment circuit operable to coarsely correct a phase error of a received inter-symbol correlated (ISC) signal, said coarsely correcting resulting in a coarse-phase-corrected received ISC signal; and

a sequence estimation circuit operable to concurrently operate on a plurality of symbols of said coarse-phase-corrected received ISC signal to:

generate an estimate of a residual phase error of said coarse-phase-corrected received ISC signal;

generate an estimate of a value of a transmitted symbol corresponding to said coarse-phase-corrected received ISC signal based on said estimate of said residual phase error;

generate one or more phase candidate vectors, each of said one or more phase candidate vectors comprising a plurality of phase values;

select a best one of said one or more phase candidate vectors as said estimate of said residual phase error of said coarse-phase-corrected received ISC signal;

calculate one or more Euclidean distances based on said one or more phase candidate vectors; and

perform said selecting of said best one of said one or more phase candidate vectors based on said one or more Euclidean distances.

12. A method comprising:

processing, in a receiver, a received inter-symbol correlated (ISC) signal, said processing resulting in a processed received ISC signal;

generating, via a sequence estimation process performed by said receiver, an estimate of a phase error of said processed received ISC signal, wherein:

said sequence estimation process concurrently operates on a plurality of symbols of said processed received ISC signal; and

said sequence estimation process comprises generating one or more phase candidate vectors, each of said one or more phase candidate vectors comprising a plurality of phase values;

generating an estimate of a value of a transmitted symbol corresponding to said received ISC signal based on said estimate of said phase error;

selecting a best one of said one or more phase candidate vectors as said estimate of said phase error of said processed received ISC signal;

calculating one or more Euclidean distances based on said one or more phase candidate vectors; and

performing said selecting of said best one of said one or more phase candidate vectors based on said one or more Euclidean distances.

13. A system comprising:

a signal processing circuit operable to process a received inter-symbol correlated (ISC) signal, said processing resulting in a processed received ISC signal; and

a sequence estimation circuit operable to concurrently operate on a plurality of symbols of said processed received ISC signal to:

generate an estimate of a phase error of said processed received ISC signal; and

generate an estimate of a value of a transmitted symbol corresponding to said received ISC signal based on said estimate of said phase error;

generate one or more phase candidate vectors, each of said phase candidate vectors comprising a plurality of phase values;

select a best one of said one or more phase candidate vectors as said estimate of said phase error of said processed received ISC signal;

calculate one or more Euclidean distances based on said one or more phase candidate vectors; and

perform said selection of said best one of said one or more phase candidate vectors based on said one or more Euclidean distances.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2017
From: MAGNACOM LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041604/0861 →
Continuity (6)
Continuation 13755039 · Jan 31, 2013
Provisional Application 61662085 · Jun 20, 2012
Provisional Application 61726099 · Nov 14, 2012
Provisional Application 61729774 · Nov 26, 2012
Provisional Application 61747132 · Dec 28, 2012
Related Publication 20140105334A1 · Apr 17, 2014