Memory system controlling load capacity
View Patent ↗A memory system includes a nonvolatile memory having a plurality of nonvolatile memory chips incorporated therein, a control circuit that controls the nonvolatile memory, an MPU that controls the control circuit, and an interface circuit that communicates with a host, all of which are mounted on a board of the memory system, and the memory system further includes a bus switch that switches connection of a signal line between the control circuit and the nonvolatile memory chips.
1. A memory system comprising:
a board;
a package for a memory mounted on the board;
a first nonvolatile memory in the package;
a second nonvolatile memory in the package;
a first signal line electrically connected to the first nonvolatile memory;
a second signal line electrically connected to the second nonvolatile memory;
an interface configured to communicate with a host;
a first controller configured to control power applied to the memory system which includes the first nonvolatile memory and the second nonvolatile memory; and
a second controller configured to control a load capacity of the first nonvolatile memory and the second nonvolatile memory according to a command from the host by controlling the first signal line and the second signal line, wherein
the second controller controls the load capacity of the first nonvolatile memory to be increased and the load capacity of the second nonvolatile memory to be reduced, when the first nonvolatile memory is accessed, while the power controlled by the first controller is applied, and
the second controller controls the load capacity of the first nonvolatile memory to be reduced and the load capacity of the second nonvolatile memory to be increased, when the second nonvolatile memory is accessed while the power controlled by the first controller is applied.
2. The memory system according to claim 1 , wherein
the second controller controls the load capacity of the first nonvolatile memory to be increased and the load capacity of the second nonvolatile memory to be reduced by electrically disconnecting the second signal line, when the first nonvolatile memory is accessed, and
the second controller controls the load capacity of the first nonvolatile memory to be reduced and the load capacity of the second nonvolatile memory to be increased by electrically disconnecting the first signal line, when the second nonvolatile memory is accessed.
3. The memory system according to claim 1 , wherein
a plurality of the first nonvolatile memories stacked on each other and a plurality of the second nonvolatile memories stacked on each other are mounted in the package,
the first signal line is electrically connected to the plurality of the first nonvolatile memories respectively, and
the second signal line is electrically connected to the plurality of the second nonvolatile memories respectively.
4. The memory system according to claim 1 , further comprising a switch configured to switch connection of the first signal line and the second signal line.
5. A memory system comprising:
a board;
a package for a memory on the board;
a first nonvolatile memory in the package;
a second nonvolatile memory in the package;
a first signal line electrically connected to the first nonvolatile memory;
a second signal line electrically connected to the second nonvolatile memory;
an interface configured to communicate with a host;
a first controller configured to control power applied to the memory system which includes the first nonvolatile memory and the second nonvolatile memory; and
a second controller configured to control a load capacity of the first nonvolatile memory according to a command from the host by controlling the first signal line and the second signal line, wherein
the second controller controls the load capacity of the first nonvolatile memory to be increased, while the power controlled by the first controller is applied, and
the second controller controls the load capacity of the first nonvolatile memory to be reduced, while the power controlled by the first controller is applied.
6. A memory system comprising:
a nonvolatile memory;
a pin for sending a control signal to the nonvolatile memory;
a signal line electrically connected to the nonvolatile memory and the pin;
an interface configured to communicate with a host;
a first controller configured to control power applied to the memory system which includes the nonvolatile memory; and
a second controller configured to control a load capacity of the non-volatile memory according to a command from the host by controlling the signal line, wherein
the second controller controls the load capacity of the nonvolatile memory to be increased, when the nonvolatile memory is accessed, while the power controlled by the first controller is applied, and
the second controller controls the load capacity of the nonvolatile memory to be reduced, when the nonvolatile memory is not accessed, while the power controlled by the first controller is applied.
7. A system including a host device comprising:
a memory device;
an interface between the host device and the memory device;
a first controller configured to control power applied to the memory device; and
a second controller configured to control a load capacity of the memory device according to a command from the host device, wherein
the second controller controls the load capacity of the memory device to be increased, while the power controlled by the first controller is applied, and
the second controller controls the load capacity of the memory device to be reduced, while the power controlled by the first controller is applied.