Methods and apparatus for providing a maximum likelihood (ML) decoding pipeline for quadruture phase-shift keying (QPSK) multiple-input-multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) receivers
View Patent ↗Methods and apparatus are provided for performing log-likelihood ratio (LLR) computations in a pipeline. Portions of a metric used to compute LLR values are computed in one pipeline part. The portions correspond to all permutations of some received signal streams. The portions are combined with one permutation x 2 of the received signal stream that was not included in the previous pipeline computation in a subsequent pipeline part to produce M values associated with a particular bit position. At each subsequent clock cycle, a different permutation of x 2 is combined with the previously computed portions producing different M values. State values corresponding to different values of bit positions of the received stream are computed by finding the minimum among the M values, in each clock cycle, that affect a particular bit position. The state values are combined to compute the LLR values for the bit position in a final pipeline part.
1. A method comprising:
generating, with control circuitry in a first pipeline stage, a first metric state portion; and
generating, with the control circuitry in a second pipeline stage following the first pipeline stage, a first metric state based on the first metric state portion, wherein the first metric state is compared to a second metric state for determining whether the second metric state is less than the first metric state.
2. The method of claim 1 , wherein the first metric state portion is based on a difference between an input signal value and a predetermined value.
3. The method of claim 1 , wherein the metric state portion is computed based on a plurality of permutations of a plurality of streams of an input signal.
4. The method of claim 1 , wherein the second metric state is generated in the second pipeline stage and is based on a second metric state portion generated in the first pipeline stage while the first metric state is generated.
5. The method of claim 1 , wherein the first pipeline stage is performed in N clock cycles and the second pipeline stage is performed during a next N clock cycles.
6. The method of claim 1 , wherein the first metric state portion corresponds to a first tone of an input signal.
7. The method of claim 1 , wherein the first metric state is compared to the second metric state by comparing a first minimum of a first plurality of metric state values with a second minimum of a second plurality of metric state values.
8. The method of claim 1 , wherein the control circuitry is in a QPSK receiver or an OFDM receiver.
9. The method of claim 2 , wherein the predetermined value is in a set of predetermined values corresponding to a plurality of permutations of a subset of a plurality of input streams and a first permutation of a remainder of the plurality of input streams.
10. The method of claim 3 , wherein the plurality of streams of the input signal are not all of the streams of the input signal.
11. A system comprising:
metric state portion computation circuitry configured to generate, in a first pipeline stage, a first metric state portion; and
metric logic circuitry configured to generate, in a second pipeline stage following the first pipeline stage, a first metric state based on the first metric state portion, wherein the first metric state is compared to a second metric state for determining whether the first metric state is less than the second metric state.
12. The system of claim 11 , wherein the first metric state portion is based on a difference between an input signal value and a predetermined value.
13. The system of claim 11 , wherein the metric state portion is computed based on a plurality of permutations of a plurality of streams of an input signal.
14. The system of claim 11 , wherein the second metric state is generated in the second pipeline stage and is based on a second metric state portion generated in the first pipeline stage while the first metric state is generated.
15. The system of claim 11 , wherein the first pipeline stage is performed in N clock cycles and the second pipeline stage is performed during a next N clock cycles.
16. The system of claim 11 , wherein the first metric state portion corresponds to a first tone of an input signal.
17. The system of claim 11 , wherein the first metric state is compared to the second metric state by comparing a first minimum of a first plurality of metric state values with a second minimum of a second plurality of metric state values.
18. The system of claim 11 , wherein the control circuitry is in a QPSK receiver or an OFDM receiver.
19. The system of claim 12 , wherein the predetermined value is in a set of predetermined values corresponding to a plurality of permutations of a subset of a plurality of input streams and a first permutation of a remainder of the plurality of input streams.
20. The system of claim 13 , wherein the plurality of streams of the input signal are not all of the streams of the input signal.