SEMICONDUCTOR DEVICE HAVING CURRENT CHANGE MEMORY CELL
A method includes performing a read operation on a memory cell of a device including a sensing line, a bit line coupled to the memory cell, a first transistor having a source-drain path coupled between the sensing line and the bit line, and a second transistor having a gate coupled to sense the sensing line, the performing including providing a gate of the first transistor with a first voltage, providing the sensing line with a second voltage, and providing the bit line with a third voltage, the third voltage being independent from the second voltage.
1 . A method comprising:
performing a read operation on a memory cell of a device comprising a sensing line, a bit line coupled to the memory cell, a first transistor having a source-drain path coupled between the sensing line and the bit line, and a second transistor having a gate coupled to sense the sensing line,
the performing comprising:
providing a gate of the first transistor with a first voltage;
providing the sensing line with a second voltage; and
providing the bit line with a third voltage, the third voltage being independent from the second voltage.
2 . The method of claim 1 , wherein the performing comprises:
refraining from providing the sense line and the bit line with the second and third voltages, respectively; and
turning the memory cell on while keeping providing the gate of the first transistor with the first voltage.
3 . The method of claim 1 , wherein the performing comprises:
sensing the sense line by using the second transistor.
4 . The method of claim 1 , wherein the performing comprises:
reading a first logic value when the second transistor is on in response to a voltage of the sensing line; and
reading a second logic value different from the first logic value when the second transistor is off in response to a voltage of the sensing line, the first and second logic values being different from each other.
5 . The method of claim 1 , wherein the first voltage is between the second voltage and the third voltage.
6 . The method of claim 1 , wherein the second voltage is larger than the third voltage.
7 . The method of claim 1 , wherein a voltage obtained by subtracting a threshold voltage of the first transistor from the first voltage is lower than the third voltage.
8 . The method of claim 1 , wherein a voltage of the bit line transitions from the third voltage toward a fourth voltage that is lower than the third voltage in accordance with data stored in the memory cell, regardless of “1” or “0” of the data.
9 . The method of claim 1 , wherein the performing comprises:
reading a first logic value from a data line coupled to the second transistor when a voltage of the bit line is below a predetermined voltage; and
reading a second logic value from the data line when a voltage of the bit line is not below the predetermined voltage, the first and second logic values being different from each other.
10 . The method of claim 1 , wherein the performing comprises:
turning the memory cell on; and
after turning the memory cell on, changing the first voltage to be a control voltage to turn the first transistor off, the control voltage being lower than the first voltage.
11 . The method of claim 10 , wherein the control voltage is a ground potential.
12 . The method of claim 1 , wherein the performing comprises:
providing a writing path conveying data to the bit line, the writing path being different from the sensing line.
13 . The method of claim 12 , wherein the writing path includes a write transistor having a source-drain path coupled between a global bit line and the bit line, and the second transistor having a source-drain path coupled between a ground potential and the global bit line.
14 . The method of claim 1 , wherein the performing comprises:
producing the first voltage to be provided to the gate of the first transistor by using a replica transistor.
15 . The method of claim 14 , wherein the first transistor and the replica transistor are a same structure as each other.
16 . A method comprising:
making an access to a memory cell of a device comprising a sensing line, a bit line coupled to the memory cell, a first transistor having a source-drain path coupled between the sensing line and the bit line, and a second transistor having a gate coupled to sense the sensing line,
the making comprising:
providing a gate of the first transistor with a first voltage;
providing the sensing line with a second voltage by using a first charge circuit; and
providing the bit line with a third voltage by using a second charge circuit, the first and second circuits being different from each other.
17 . The method of claim 16 , wherein the first charge circuit includes a third transistor having a source-drain path coupled between a first line supplying the second voltage and the sensing line, and the second charge circuit includes a fourth transistor having a source-drain path coupled between a second line supplying the third voltage and the bit line.
18 . The method of claim 16 , wherein the first voltage is between the second voltage and the third voltage.
19 . The method of claim 16 , wherein the second voltage is larger than the third voltage.
20 . The method of claim 16 , wherein a voltage obtained by subtracting a threshold voltage of the first transistor from the first voltage is lower than the third voltage.