System and method of improving stability of continuous-time delta-sigma modulators
View Patent ↗An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.
1. A calibration system, comprising:
a continuous-time delta sigma analog-to-digital converter (ADC) that receives an analog input and converts the analog input to digital data;
a data monitor that parses the digital data to produce an output; and
calibration logic configured to adjust stability parameters of the ADC, at least based on the output of the data monitor, wherein the stability parameters include at least one of a direct feedback coefficient of the ADC and a flash digital-to-analog converter (DAC) timing coefficient of the ADC.
2. The calibration system of claim 1 , wherein the calibration logic adjusts the stability parameters by changing at least one of a bias current, a component value, and a reference voltage.
3. The calibration system of claim 1 , wherein the data monitor is implemented as a a digital power meter, and the data monitor calculates a sum of squares of values of the digital data, calculates a sum of absolute values of values of the digital data, or sub-samples values of the digital data.
4. The calibration system of claim 1 , wherein the calibration logic is implemented on an embedded programmable microprocessor, is implemented on-chip with the ADC by an application-specific integrated circuit (ASIC), or is implemented off-chip with a system including software.
5. The calibration system of claim 1 , wherein the calibration logic either implements a linear search between two ranges or implements a hill climbing algorithm to choose a stability code for the ADC that results in the ADC producing a minimum root mean square (RMS) power.
6. The calibration system of claim 1 , wherein the calibration logic implements an algorithm to choose a stability code for the ADC that results in the ADC producing a minimum root mean square (RMS) power, the algorithm being one of a simulated annealing algorithm, a genetic algorithm, or a random search.
7. A method implemented by a calibration system, the method comprising:
converting, with a continuous-time delta sigma analog-to-digital converter (ADC), an analog input to digital data;
parsing, with a data monitor, the digital data to produce an output; and
adjusting, with calibration logic, stability parameters of the ADC, at least based on the output of the data monitor, wherein the stability parameters include at least one of a direct feedback coefficient of the ADC and a flash digital-to-analog converter (DAC) timing coefficient of the ADC.
8. The method of claim 7 , wherein the adjusting adjusts the stability parameters by changing at least one of a bias current, a component value, and a reference voltage.
9. The method of claim 7 , wherein the data monitor is implemented as a digital power meter, and the parsing calculates a sum of squares of values of the digital data, calculates a sum of absolute values of values of the digital data, or sub-samples values of the digital data.
10. The method of claim 7 , wherein the calibration logic is implemented on an embedded programmable microprocessor, is implemented on-chip with the ADC by an application-specific integrated circuit (ASIC), or is implemented off-chip with a system including software.
11. The method of claim 7 , further comprising:
implementing a linear search between two ranges or implementing a hill climbing algorithm to choose a stability code for the ADC that results in the ADC producing a minimum root mean square (RMS) power.
12. The method of claim 7 , further comprising:
implementing an algorithm to choose a stability code for the ADC that results in the ADC producing a minimum root mean square (RMS) power, the algorithm being one of a simulated annealing algorithm, a genetic algorithm, or a random search.
13. Logic encoded in one or more non-transitory media that includes code for execution and, when executed by a processor, operable to perform operations comprising:
receiving an output from a data monitor; and
adjusting stability parameters of a continuous-time delta sigma analog-to-digital converter (ADC), at least based on the output of the data monitor, wherein the ADC converts an analog input to digital data, and the stability parameters include at least one of a direct feedback coefficient of the ADC and a flash digital-to-analog converter (DAC) timing coefficient of the ADC.
14. The logic of claim 13 , wherein the adjusting adjusts the stability parameters by changing at least one of a bias current, a component value, and a reference voltage.
15. The logic of claim 13 , wherein the processor is an embedded programmable microprocessor, is an application-specific integrated circuit (ASIC) on-chip with the ADC, or is a processor off-chip from the ADC in a system including software.
16. The logic of claim 13 , the operations further comprising:
implementing an algorithm to choose a stability code for the ADC to increase a stability of the ADC, the algorithm being one of a linear search between two ranges, a hill climbing algorithm, a simulated annealing algorithm, a genetic algorithm, or a random search.
17. The logic of claim 13 , the operations further comprising:
setting a stability parameter of the ADC in response to a determination that a stability of the ADC is greater than a previous stability of the ADC.