IP Library Granted Patent US 9,087,783
Granted Patent B2
US 9,087,783 · App. 14/066,416 · Granted Jul 21, 2015

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 9,087,783
App. No.
14/066,416
Granted
Jul 21, 2015
Kind
B2
Abstract

A hard mask formed above a gate film is patterned with a first mask pattern, the patterned hard mask film is processed into a gate pattern with a second mask pattern, the gate film is patterned with the hard mask film as a mask, a spacer insulating film is formed, a third mask pattern covering an edges of the gate pattern is formed above the spacer insulating film, the spacer insulating film is etched with the third mask pattern as a mask, and a sidewall insulating film is formed on side walls of the gate film leaving the spacer insulating film in a region of the edge of the gate pattern.

Claims (33)

1. A method of manufacturing a semiconductor device comprising:

forming a gate insulating film above a semiconductor substrate;

forming a gate film above the gate insulating film;

forming a hard mask film above the gate insulating film;

patterning the hard mask with a first mask pattern;

processing the patterned hard mask film into a gate pattern with a second mask pattern;

patterning the gate film and the gate insulating film with the hard mask film having the gate pattern as a mask;

forming a spacer insulating film above the semiconductor substrate with the patterned gate film and the gate insulating film;

forming above the spacer insulating film a third mask pattern covering an edge of the patterned gate film and the gate insulating film; and

etching the spacer insulating film with the third mask patterns as the mask to form a sidewall insulating film of the spacer insulating film on side walls of the patterned gate film and the gate insulating film, leaving the spacer insulating film below the third mask pattern.

2. The method of manufacturing a semiconductor device according to claim 1 , wherein

the third mask pattern has an inverted pattern of the second mask pattern.

3. The method of manufacturing a semiconductor device according to claim 1 , wherein

the gate insulating film includes a high dielectric constant insulating film.

4. The method of manufacturing a semiconductor device according to claim 1 ,

further comprising, before forming the gate insulating film, forming a device isolation insulating film defining an active region, and in which

a region where the second mask pattern is exposed is positioned on the device isolation insulating film.

5. The method of manufacturing a semiconductor device according to claim 4 , further comprising after removing the third mask pattern:

exposing the semiconductor substrate in the active region with a chemical processing, and

forming a silicide film above the active region where the semiconductor substrate is exposed.

6. The method of manufacturing a semiconductor device according to claim 4 , further comprising after removing the third mask pattern:

removing the hard mask film;

removing the gate film; and

burying a metal material in a part from which the gate film has been removed to form a gate electrode of the metal material.

7. The method of manufacturing a semiconductor device according to claim 6 , further comprising after forming the gate insulating film and before forming the gate film:

forming a buffer layer, in which

in removing the gate film, the gate film is removed with the buffer layer as a stopper.

8. The method of manufacturing a semiconductor device according to claim 1 , wherein

the hard mask film includes a first hard mask film and a second hard mask film formed on the first hard mask film,

in patterning the hard mask film, the second hard mask film is patterned with the first hard mask film as a stopper, and

in patterning the gate film and the gate insulating film, the first hard mask film, the gate film and the gate insulating film are patterned with the second hard mask film as a mask.

9. The method of manufacturing a semiconductor device according to claim 1 , wherein

in processing the hard mask film with the second mask pattern, a plurality of gate patterns are formed.

Assignments (2)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2013
From: FUKUDA, MASATOSHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 031504/0001 →