Patent Application

App. No. 14/067,444

Abstract

Claims (33)

1 . A method of simulation and design verification of an audio device, comprising:

capturing a plurality of signals in a data collection system, the plurality of signals including input signals for an audio processor;

providing a high-level language (HLL) model, the HLL model including inputs and outputs that match the plurality of signals, the HLL model comprised of a plurality of blocks having inputs and outputs that are interconnected in a net list of the HLL model to implement a block level functionality of the audio processor, the plurality of blocks including

input blocks including a radio frequency (RF) receive (Rx) audio block, a first microphone block, a second microphone block, and a surface skin microphone block,

output blocks including a RF transmit (Tx) audio block and a speaker block, and

signal processing blocks including a noise suppression block, a first automatic echo cancellation (AEC) block, a second AEC block, and a voice activity detector (VAD) block;

providing a plurality of optimized operator modules (OOM) coded in a format for a target hardware platform, each optimized operator module is coded to implement the function of a corresponding block in the plurality of blocks and receives data inputs and generates data outputs corresponding to the inputs and outputs of its corresponding block;

compiling the plurality of optimized operator modules to implement functionality of the audio processor as interconnected in the net list of the HLL model;

executing the HLL model on a HLL simulation tool configured to apply the input signals from the plurality of signals to the inputs of the HLL model, to process the input signals according the function implemented by each block, and to generate simulated output signals on the outputs of the HLL model; and

analyzing the simulated output signals to determine how closely the HLL model meets a performance criteria for the audio processor.

2 . The method of claim 1 , wherein the target hardware platform comprises an integrated circuit (IC) selected from the group consisting of a controller, a multi-core controller, a processor, a multi-core processor, a digital signal processor (DSP), a multi-core DSP, a system on chip (SoC), a multi-core SoC, an application specific IC (ASIC), and a field programmable gate array (FPGA).

3 . The method of claim 1 , wherein providing the plurality of optimized operator modules comprises selecting a ported library module from a target hardware library that includes a plurality of ported library modules, with each ported library module including a unique plurality of optimized operator modules coded in a format for a unique target hardware platform.

4 . The method of claim 1 , wherein the format for the target hardware platform comprises assembly language.

5 . The method of claim 1 , wherein compiling the plurality of optimized operator modules generates an executable code configured to execute on one or more processors in the target hardware platform, the executable code embodied in a non-transitory computer readable medium that is electrically accessed by the one or more processors.

6 . The method of claim 5 and further comprising:

executing the executable code on the one or more processors while applying the input signals from the plurality of signals to input ports of the target hardware platform; and

analyzing hardware output signals from output ports of the target hardware platform to determine how closely the plurality of optimized operator modules meets the performance criteria for the audio processor.

7 . The method of claim 6 , wherein the analyzing hardware output signals comprises comparing the hardware output signals with the simulated output signals.

8 . The method of claim 7 and further comprising: revising one or more blocks in the plurality of blocks, one or more optimized operator modules in the plurality of optimized operator modules or both, when the comparing indicates the HLL model, the executable code or both do not meet the performance criteria.

9 . The method of claim 1 , wherein the signal processing blocks include an equalization and processing block coupled between the RF Rx audio block and the speaker block.

10 . The method of claim 1 , wherein the signal processing blocks include a speech state detector block.

11 . The method of claim 1 , wherein the plurality of signals includes one or more output signals.

12 . The method of claim 1 , wherein the first AEC block is included in the noise suppression block.

13 . The method of claim 1 , wherein the second AEC block is included in the VAD block.

14 . The method of claim 1 , wherein the speaker block includes a first output coupled with the first AEC block and a second output coupled with the second AEC block.

15 . The method of claim 1 , wherein the RF Tx audio block is coupled with an output from the noise suppression block.

16 . The method of claim 1 , wherein the RF Rx audio block, the first microphone block, the second microphone block, and the surface skin microphone block are inputs to the noise suppression block.

17 . The method of claim 1 , wherein the surface skin microphone block is an input to the first AEC block and the second AEC block.

18 . The method of claim 1 , wherein at least one of the plurality of blocks comprises a macro from a HLL library.

19 . The method of claim 1 , wherein the signal processing blocks include a wind noise reduction block.

20 . The method of claim 1 and further comprising:

a wireless media device that includes the audio processor, the wireless media device is instantiated in the net list of the HLL model, HLL blocks for the wireless media device comprises a portion of the plurality of blocks, and OOM's for the wireless media device comprises a portion of the plurality of OOM's.

21 . (canceled)

Assignments (16)