SINGLE LOCAL OSCILLATOR ARCHITECTURE
A system and method in a transceiver for reducing power. In transmission mode (Tx), a local oscillator (LO) generator (LOGEN) circuit modifies a PLL oscillation signal that runs at a fraction of the carrier signal. In the receive mode (Rx), the LOGEN circuit increases power consumption unnecessarily and is bypassed in favor of a PLL output which is a multiple of the carrier signal.
1 . A transceiver comprising:
a receiver processing chain including at least a down-converter;
a transmission processing chain including at least an up-converter;
a phase lock loop coupled to both the down-converter and the up-converter; and
wherein the phase lock loop is configured, in a receive mode, to generate a first output oscillation signal at a multiple of a carrier frequency and, in a transmit mode, to generate a second output oscillation signal at a fraction of the carrier frequency.
2 . The transceiver according to claim 1 , wherein the phase lock loop is further configured to generate the first output oscillation to have a frequency that is two times the frequency of the carrier frequency.
3 . The transceiver according to claim 1 further comprising a divider to reduce the first output oscillation signal by the multiple and coupling to the down-converter.
4 . The transceiver according to claim 1 further comprising circuitry to convert the fraction of the carrier frequency to a third output signal, which is a multiple of the carrier frequency.
5 . The transceiver according to claim 4 further comprising a divider to reduce the third output signal by the multiple and coupling to the up-converter.
6 . The transceiver according to claim 1 , wherein the transceiver further comprises Bluetooth circuitry for facilitating Bluetooth communications.
7 . The transceiver according to claim 1 further comprising the transmission processing chain comprising a first and second transmission path, the first transmission path generating a constant envelope from the first output oscillation signal and the second path generating a variable envelope using the second output oscillation signal.
8 . The transceiver according to claim 7 , wherein the first and second paths are further configured to operate independently of each other and wherein one or more circuit elements of the second path are powered down during operation of the first path and one or more circuit elements of the first path are powered down during operation of the second path.
9 . The transceiver according to claim 1 , wherein the down-converter is configured to down-convert a received signal to an intermediate frequency signal.
10 . The transceiver according to claim 9 , further comprising a digital signal processor configured to digitally down-convert the intermediate frequency signal.
11 . The transceiver according to claim 9 , further comprising a digital signal processor configured to digitally phase adjust the intermediate frequency signal.
12 . A transceiver comprising:
a receiver processing chain including at least a down-converter;
a first transmission processing chain generating a constant envelope transmission signal;
a second transmission processing chain including at least an up-converter and generating a variable envelope;
a phase lock loop coupled to the receiver and first and second transmission processing chains; and
wherein the phase lock loop is configured in: a receive mode to generate a first output oscillation signal at a multiple of a carrier frequency; a first transmit mode to generate the constant envelope using the multiple of the carrier frequency; and a second transmit mode generating the variable envelope using a second output oscillation signal at a fraction of the carrier frequency.
13 . The transceiver according to claim 12 , wherein the phase lock loop is further configured to generate the first output oscillation to have a frequency that is two times the frequency of the carrier frequency.
14 . The transceiver according to claim 12 further comprising a divider to reduce the first output oscillation signal by the multiple and coupling to the down-converter.
15 . The transceiver according to claim 12 , wherein the a second transmission processing chain further includes a local oscillator generator (LOGEN) to convert the fraction of the local oscillator frequency to a third output signal which is a multiple of the carrier frequency.
16 . The transceiver according to claim 15 further comprising a divider to reduce the third output signal by the multiple and coupling to the up-converter.
17 . The transceiver according to claim 12 , wherein the transceiver further comprises Bluetooth circuitry for facilitating Bluetooth communications.
18 . A frequency-division duplex transceiver comprising:
a duplexer for receiving bi-directional communication signals including a receive signal and transmit signal;
a receiver processing chain including at least a down-converter;
a transmission processing chain including at least an up-converter;
a phase lock loop shared by the receiver and transmission processing chains, the phase lock loop configured to generate an output oscillation signal at a multiple of the carrier frequency;
a digital signal processor; and
wherein the transceiver is configured to down-convert the receive signal to an intermediate frequency followed by the digital signal processor digitally down-converting the intermediate frequency and up-convert the transmit signal.
19 . The frequency-division duplex transceiver according to claim 18 , further comprising the digital signal processor configured to digitally phase adjust the intermediate frequency signal.
20 . The frequency-division duplex transceiver according to claim 18 , wherein the frequency-division duplex transceiver further comprises Bluetooth circuitry for facilitating Bluetooth communications.