Integrated circuit for controlling a process
View Patent ↗Wireless communication wherein channel estimation accuracy is improved while keeping the position of each bit in a frame, even when a modulation system having a large modulation multiple value is used for a data symbol. An encoding operation encodes and outputs transmitting data (bit string) and a bit converting operation converts at least one bit of a plurality of bits constituting a data symbol to be used for channel estimation, among the encoded bit strings, into ‘1’ or ‘0’. A modulating operation modulates the bit string inputted from the bit converting operation by using a single modulation mapper and a plurality of data symbols are generated.
1. An integrated circuit for controlling a process comprising:
receiving control information indicating a number of bits to be converted;
generating a bit sequence by converting each of the number of bits indicated by the control information of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and
modulating the bit sequence by mapping the plurality of bits on a single modulation mapper, the single modulation mapper having first signal points,
wherein each of the number of bits is converted to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are apart of the first signal points, a distance between the second signal points being equivalent to a largest of distances existing among the first signal points in an I-Q plane of the single modulation mapper.
2. The integrated circuit according to claim 1 , wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.
3. The integrated circuit according to claim 1 , wherein the control information indicates two as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest two bits of the plurality of bits to the 1.
4. The integrated circuit according to claim 1 , wherein the control information indicates three as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest three bits of the plurality of bits to the 1.
5. The integrated circuit according to claim 1 , wherein the control information indicates four as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest four bits of the plurality of bits to the 1.
6. An integrated circuit for controlling a process comprising:
receiving control information indicating a number of bits to be converted;
generating a bit sequence by converting each of the number of bits indicated by the control information of a plurality of bits to a 1, the plurality of bits forming a modulation symbol in the bit sequence; and
modulating the bit sequence by mapping the plurality of bits on a single modulation mapper, the single modulation mapper having first signal points,
wherein each of the number of bits is converted to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are apart of the first signal points, such that said modulation symbol is detected by positive or negative decision only with respect to at least one of an I-axis and a Q-axis in the single modulation mapper.
7. The integrated circuit according to claim 6 , wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.
8. The integrated circuit according to claim 6 , wherein the control information indicates two as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest two bits of the plurality of bits to the 1.
9. The integrated circuit according to claim 6 , wherein the control information indicates three as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest three bits of the plurality of bits to the 1.
10. The integrated circuit according to claim 6 , wherein the control information indicates four as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest four bits of the plurality of bits to the 1.
11. An integrated circuit for controlling a process:
transmitting control information indicating a number of bits to be converted; and
receiving a bit sequence, in which each of the number of bits indicated by the control information of a plurality of bits is converted to a 1 and which is modulated by mapping the plurality of bits on a single modulation mapper, wherein the plurality of bits forms a modulation symbol in the bit sequence, and the single modulation mapper has first signal points,
wherein each of the number of bits is converted to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are apart of the first signal points, a distance between the second signal points being equivalent to a largest of distances existing among the first signal points in an I-Q plane of the single modulation mapper.
12. The integrated circuit according to claim 11 , wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.
13. The integrated circuit according to claim 11 , wherein the control information indicates two as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest two bits of the plurality of bits to the 1.
14. The integrated circuit according to claim 11 , wherein the control information indicates three as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest three bits of the plurality of bits to the 1.
15. The integrated circuit according to claim 11 , wherein the control information indicates four as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest four bits of the plurality of bits to the 1.
16. An integrated circuit for controlling a process comprising:
transmitting control information indicating a number of bits to be converted; and
receiving a bit sequence, in which each of the number of bits indicated by the control information of a plurality of bits is converted to a 1 and which is modulated by mapping the plurality of bits on a single modulation mapper, wherein the plurality of bits forms a modulation symbol in the bit sequence, and the single modulation mapper has first signal points,
wherein each of the number of bits is converted to the 1 in a way that the plurality of bits are mapped to one of second signal points, which are apart of the first signal points, such that said modulation symbol is detected by positive or negative decision only with respect to at least one of an I-axis and a Q-axis in the single modulation mapper.
17. The integrated circuit according to claim 16 , wherein the single modulation mapper has 16 first signal points for 16 QAM, and the second signal points are a constellation of BPSK, QPSK or 8-PSK which is included in the single modulation mapper.
18. The integrated circuit according to claim 16 , wherein the control information indicates two as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest two bits of the plurality of bits to the 1.
19. The integrated circuit according to claim 16 , wherein the control information indicates three as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest three bits of the plurality of bits to the 1.
20. The integrated circuit according to claim 16 , wherein the control information indicates four as the number of bits to be converted, and the bit sequence is generated by converting each of the lowest four bits of the plurality of bits to the 1.