Method and system for fast synchronized dynamic switching of a reconfigurable phase locked loop (PLL) for near field communications (NFC) peer to peer (P2P) active communications

1. A reconfigurable circuit comprising:

a pause detector mechanism;

a clock extractor;

a multiplexer configured to receive a reference clock and coupled to the clock extractor to receive a clock extracted from a carrier of a near field communication (NFC) field; and

a phase locked loop (PLL) coupled to pause detector mechanism and the multiplexer, wherein the PLL can be configured in a first mode to be locked to the reference clock, in a second mode to be locked to the extracted clock, and in a third mode wherein the PLL can switch between being locked to the reference clock and being locked to the extracted clock.

2. The reconfigurable circuit of claim 1 , wherein in the first mode the PLL is configured as a fractional-N PLL.

3. The reconfigurable circuit of claim 1 , wherein in the second mode the PLL is configured as a carrier recovery PLL.

4. The reconfigurable circuit of claim 1 , wherein in the third mode the PLL is configured as a carrier recovery PLL which is locked to the extracted clock during data reception and is configured as a fractional-N PLL to generate an NFC field from the reference clock once data has been demodulated by the target.

5. The reconfigurable circuit of claim 4 , wherein the reference clock to baseband path remains continuous throughout communication.

6. The reconfigurable circuit of claim 1 , wherein the PLL comprises:

a phase frequency detector (PFD);

a charge pump coupled to the PFD;

a loop filter coupled to the charge pump; and

a voltage controlled oscillator (VCO) coupled to the loop filter.

7. The reconfigurable circuit of claim 1 , wherein the first mode comprises a reader mode, the second mode comprises a card mode and the third mode comprises a peer to peer mode.

8. The reconfigurable circuit of claim 7 includes a local oscillator (LO) divider coupled to the VCO.

9. The reconfigurable circuit of claim 8 includes a digital baseband control mechanism coupled in feedback relationship between the VCO and the PFD.

10. The reconfigurable circuit of claim 1 , wherein the clock extractor is used to close the PLL loop only if an NFC field is present and a valid clock signal is detected from another NFC device.

11. A method for reconfiguring a phase locked loop (PLL) comprising:

configuring the PLL in a first mode to be locked to the reference clock;

configuring the PLL in a second mode to be locked to a clock extracted from a carrier of a near field communication (NFC) field; and

configuring the PLL in a third mode such that the PLL can switch between being locked to the reference clock and being locked to the extracted clock.

12. The method of claim 11 , wherein the first mode comprises a reader mode, the second mode comprises a card mode and the third mode comprises a peer to peer mode.

13. The reconfigurable circuit of claim 11 , wherein in the first mode the PLL is configured as a fractional-N PLL.

14. The reconfigurable circuit of claim 13 wherein in the second mode the PLL is configured as a carrier recovery PLL.

15. The reconfigurable circuit of claim 14 , wherein in the third mode the PLL is configured as a carrier recovery PLL which is locked to the extracted clock during data reception and is configured as a fractional-N PLL to generate an NFC field from the reference clock once data has been demodulated by the target.

16. The reconfigurable circuit of claim 11 , wherein the reference clock to baseband path remains continuous throughout communication.

17. The method of claim 11 wherein a PLL loop is closed only if an NFC field is present and a valid clock signal is detected from another NFC device.