Ion sensitive field effect transistor

1. A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising:

an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor,

a dielectric material over a semiconductor substrate comprising a drain and a source wherein the dielectric material is in contact with, or surrounds, the recess, and

wherein the dielectric material further includes an inter-layer dielectric on top of the substrate, the inter-layer dielectric at least partially covering the gate.

2. An ISFET according to claim 1 , wherein the recess is formed directly on top of the gate.

3. An ISFET according to claim 1 , wherein at least one layer is formed between the recess and the gate, the at least one layer comprising a material comprising any of titanium nitride, silicon oxide nitride, silicon oxide or a metal.

4. An ISFET according to claim 1 , wherein the gate comprises an insulator.

5. An ISFET according to claim 1 , wherein the gate comprises an insulator and poly gate on top of the insulator.

6. An ISFET according to claim 1 , wherein the recess comprises an ion sensitive membrane.

7. An ISFET according to claim 1 , wherein the dielectric material further comprises at least one inter-metal dielectric on top of the inter-layer dielectric.

8. An ISFET according to claim 1 , wherein the ISFET is a bipolar based ISFET.

9. An ISFET according to claim 6 , wherein the ion sensitive membrane is deposited on at least a portion of the surface defining the recess on top of the gate.

10. An ISFET according to claim 7 , further comprising inter metals formed within the at least one inter-metal dielectric, the inter metals being connected separately with the source and drain by contact plugs.

11. An ISFET according to claim 10 , wherein the recess is formed on top of the inter-layer dielectric.

12. An ISFET according to claim 10 , wherein the recess is formed on top of a first inter-metal dielectric.

13. An ISFET according to claim 10 further comprising a passivation layer formed on top of the at least one inter-metal layer, wherein the passivation layer is in contact with, or surrounds, the recess.

14. A method of manufacturing an Ion Sensitive Field Effect Transistor (ISFET) utilizing CMOS or bipolar processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor, wherein the recess is formed by patterning a dielectric material on top of the gate and etching the dielectric material, and wherein the gate has direct contact with the recess.

15. A method according to claim 14 , wherein the recess is formed directly on top of the gate.

16. A method according to claim 14 , wherein the gate comprises an insulator.

17. A method according to claim 14 , wherein the gate comprises an insulator and a poly gate on top of the insulator.

18. A method according to claim 14 , wherein the recess is formed utilizing CMOS or bipolar processing steps.

19. A method of manufacturing an Ion Sensitive Field Effect Transistor (ISFET) utilizing CMOS or bipolar processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor, wherein the transistor comprises a CMOS or bipolar device having inter-layer metals, a dielectric region having dielectric layers and a passivation layer over a semiconductor substrate of the device, and wherein the gate has direct contact with the recess.

20. A method according to claim 19 , wherein the CMOS or bipolar device is formed by:

providing the semiconductor substrate having a source and a drain;

providing the gate on top of the substrate between the source and the drain;

providing the dielectric region comprising an inter-layer dielectric over the substrate and inter-metal dielectrics on top of the inter-layer dielectric;

providing the inter-layer metals in each inter-layer dielectric over the source and drain, the inter-layer metals being connected separately with the source and drain by contact plugs and being connected with one another by inter-layer vias; and

providing the passivation layer over the inter-layer metals and the inter-metal dielectrics.

21. A method according to claim 19 , wherein the recess is formed by patterning the dielectric region on top of the gate and etching the dielectric layers of the dielectric region.

22. A method according to claim 21 , wherein etching the dielectric region on top of the gate comprises:

etching a portion of the passivation layer over the gate;

etching a portion of the inter-metal dielectrics over the gate; and

etching a portion of the inter-layer dielectric on top of the gate.

23. A method according to claim 21 , wherein etching the dielectric region on top of the gate comprises:

etching a portion of the passivation layer over the gate; and

etching a portion of the inter-metal dielectrics over the gate.

24. A method of manufacturing an Ion Sensitive Field Effect Transistor (ISFET) utilizing CMOS or bipolar processing steps, the method comprising:

forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor; and

depositing an ion sensitive membrane on at least a portion of the surface defining the recess on top of the gate;

wherein the gate has direct contact with the recess.

25. An assembly comprising:

a CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor, and

a circuit for reading out a signal from the ISFET,

wherein the circuit and the ISFET are integrated within a same chip, and

wherein the gate has direct contact with the recess.