Reference voltage stabilizer circuit and integrated circuit including the same
View Patent ↗A reference voltage is maintained stable against disturbance noise and self-noise of an internal circuit. A reference voltage stabilizer circuit for stabilizing the reference voltage to be supplied through at least one of first or second signal lines includes a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and a subsequent-stage circuit including a resistive path connected between the first and second signal lines, and a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied.
1. A reference voltage stabilizer circuit for stabilizing a reference voltage to be supplied through at least one of first or second signal lines, comprising:
a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and
a subsequent-stage circuit including
a transistor inserted into one of the first or second signal lines through which the reference voltage is supplied and having a gate to which a bias voltage is applied,
a bias generator circuit configured to generate the bias voltage, and
a capacitive element connected between the gate of the transistor and the other one of the first or second signal lines into which the transistor is not inserted,
wherein the subsequent-stage circuit further includes a resistive path connected between a source of the transistor and the other one of the first or second signal lines.
2. A reference voltage stabilizer circuit for stabilizing a reference voltage to be supplied through at least one of first or second signal lines, comprising:
a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and
a subsequent-stage circuit including
a transistor inserted into one of the first or second signal lines through which the reference voltage is supplied and having a gate to which a bias voltage is applied,
a bias generator circuit configured to generate the bias voltage, and
a capacitive element connected between the gate of the transistor and the other one of the first or second signal lines into which the transistor is not inserted,
wherein the subsequent-stage circuit further includes a resistive circuit inserted, between the capacitive path and the capacitive element, into the other one of the first or second signal lines.
3. The reference voltage stabilizer circuit of claim 1 , wherein
the resistive path includes a transistor having a gate to which a bias voltage is applied, and
the subsequent-stage circuit further includes
a bias generator circuit configured to generate the bias voltage depending on a voltage between both ends of the resistive path, and
a capacitive element connected between a drain and the gate of the transistor of the resistive path.
4. The reference voltage stabilizer circuit of claim 1 , wherein the resistive path includes a resistive element.
5. The reference voltage stabilizer circuit of claim 2 , wherein the resistive circuit includes a resistive element.
6. The reference voltage stabilizer circuit of claim 2 , wherein
the resistive circuit includes a transistor having a gate to which the bias voltage is applied.
7. An integrated circuit, comprising:
the reference voltage stabilizer circuit of claim 1 ; and
an AD converter configured to convert an input analog signal into a digital signal with reference to the reference voltage stabilized by the reference voltage stabilizer circuit.
8. An integrated circuit, comprising:
the reference voltage stabilizer circuit of claim 2 ; and
an AD converter configured to convert an input analog signal into a digital signal with reference to the reference voltage stabilized by the reference voltage stabilizer circuit.
9. An integrated circuit, comprising:
a reference voltage stabilizer circuit for stabilizing a reference voltage to be supplied through at least one of first or second signal lines;
an AD converter configured to convert an input analog signal into a digital signal with reference to the reference voltage stabilized by the reference voltage stabilizer circuit; and
a regulator configured to generate the reference voltage, wherein:
the reference voltage stabilizer circuit comprises:
a preceding-stage circuit including a capacitive path connected between the first and second signal lines; and
a subsequent-stage circuit including:
a resistive path connected between the first and second signal lines, and
a resistive circuit inserted, between the capacitive path and the resistive path, into one of the first or second signal lines through which the reference voltage is supplied, and
the regulator performs a feedback control of the reference voltage depending on an error between a voltage difference between the first and second signal lines and a predetermined voltage.
10. The integrated circuit of claim 9 , further comprising:
an input switcher configured to switch input of the AD converter; and
a gain error corrector configured to correct, for the digital signal output from the AD converter, an AD conversion gain error of the AD converter.