Methods circuits apparatuses and systems for sensing a logical state of a non-volatile memory cell and non-volatile memory devices produced accordingly
View Patent ↗Disclose is a non-volatile memory (NVM) cell sensing circuit. The sensing circuit may include a sense-side-line conditioning circuit segment adapted to condition a sense-side-line of the NVM cell. Conditioning may include adjusting a charge density within the NVM cell sense-side-line during a first NVM cell current sensing phase. The conditioning circuit segment may also be adapted to maintain an NVM cell current sensing condition during a second NVM cell current sensing phase. Adjusting a charge density within the NVM cell sense-side-line may include inducing current in the sense-side-line in a direction opposite to the sensing current.
1. A non-volatile memory (NVM) cell sensing circuit comprising:
a sense-side-line conditioning circuit segment adapted to condition a sense-side-line of the NVM cell by adjusting a charge density within the NVM cell sense-side-line during a first NVM cell current sensing phase and further adapted to maintain an NVM cell current sensing condition during a second NVM cell current sensing phase, wherein adjusting a charge density within the NVM cell sense-side-line includes inducing current in the sense-side-line in a direction opposite to the sensing current.
2. The sensing circuit according to claim 1 , wherein said sense-side-line conditioning circuit segment comprises a condition current branch adapted to generate a first current during the first sensing phase and a second current, smaller than the first current, during the second sensing phase.
3. The sensing circuit according to claim 2 , wherein said conditioning current branch comprises one or more current sources when said sensing circuit is operating according to a source-side sensing arrangement.
4. The sensing circuit according to claim 2 , wherein said conditioning current branch comprises one or more current sinks when said sensing circuit is operating according to a drain-side sensing arrangement.
5. The sensing circuit according to claim 1 , wherein said sense-side-line conditioning circuit segment comprises a sense-current reservoir adapted to pinch off current flow during the first current sensing phase and to provide for substantially uninhibited flow of NVM cell current during the second current sensing phase.
6. The sensing circuit according to claim 5 , wherein said current reservoir comprises a controllable current sink when said sensing circuit is operating according to a source-side sensing arrangement.
7. The sensing circuit according to claim 5 , wherein said current reservoir comprises a controllable current source when said sensing circuit is operating according to a drain-side sensing arrangement.
8. The sensing circuit according to claim 1 , further comprising a sense current measurement circuit adapted to induce within a constituent branch a current whose amplitude is directly related the NVM cell current.
9. The sensing circuit according to claim 8 , wherein said sense current measurement circuit comprises two mirroring circuit branches, each of which is coupled in a current mirroring arrangement with a corresponding branch of said sense-side-line conditioning circuit segment.
10. A non-volatile memory (NVM) system comprising:
a non-volatile memory array including a set of NVM cells;
a sense-side-line conditioning circuit segment adapted to condition a sense-side-line of an NVM cell by adjusting a charge density within the NVM cell sense-side-line during a first NVM cell current sensing phase and further adapted to maintain an NVM cell current sensing condition during a second NVM cell current sensing phase, wherein adjusting a charge density within the NVM cell sense-side-line includes inducing current in the sense-side-line in a direction opposite to the sensing current; and
a processor configured to access said non-volatile memory array and read stored data.
11. The device according to claim 10 , wherein said sense-side-line conditioning circuit segment comprises a condition current branch adapted to generate a first current during the first sensing phase and a second current, smaller than the first current, during the second sensing phase.
12. The device according to claim 11 , wherein said conditioning current branch comprises one or more current sources when said sensing circuit is operating according to a source-side sensing arrangement.
13. The device according to claim 11 , wherein said conditioning current branch comprises one or more current sinks when said sensing circuit is operating according to a drain-side sensing arrangement.
14. The device according to claim 10 , wherein said sense-side-line conditioning circuit segment comprises a sense-current reservoir adapted to pinch off current flow during the first current sensing phase and to provide for substantially uninhibited flow of NVM cell current during the second current sensing phase.
15. The device according to claim 14 , wherein said current reservoir comprises a controllable current sink when said sensing circuit is operating according to a source-side sensing arrangement.
16. The device according to claim 14 , wherein said current reservoir comprises a controllable current source when said sensing circuit is operating according to a drain-side sensing arrangement.
17. The device according to claim 10 , further comprising a sense current measurement circuit adapted to induce within a constituent branch a current whose amplitude is directly related the NVM cell current.
18. The device according to claim 17 , wherein said sense current measurement circuit comprises two mirroring circuit branches, each of which is coupled in a current mirroring arrangement with a corresponding branch of said sense-side-line conditioning circuit segment.
19. A non-volatile memory (NVM) cell sensing method comprising:
conditioning a sense-side-line of the NVM cell by adjusting a charge density within the NVM cell sense-side-line during a first NVM cell current sensing phase;
maintaining an NVM cell current sensing condition during a second NVM cell current sensing phase; and
wherein adjusting a charge density within the NVM cell sense-side-line includes inducing current in the sense-side-line in a direction opposite to the sensing current.
20. The method according to claim 19 , wherein said sense-side-line conditioning circuit segment comprises a condition current branch adapted to generate a first current during the first sensing phase and a second current, smaller than the first current, during the second sensing phase.
21. The method according to claim 20 , wherein said conditioning current branch comprises one or more current sources when said sensing circuit is operating according to a source-side sensing arrangement.
22. The method according to claim 20 , wherein said conditioning current branch comprises one or more current sinks when said sensing circuit is operating according to a drain-side sensing arrangement.
23. The method according to claim 19 , wherein said sense-side-line conditioning circuit segment comprises a sense-current reservoir adapted to pinch off current flow during the first current sensing phase and to provide for substantially uninhibited flow of NVM cell current during the second current sensing phase.
24. The method according to claim 23 , wherein said current reservoir comprises a controllable current sink when said sensing circuit is operating according to a source-side sensing arrangement.
25. The method according to claim 23 , wherein said current reservoir comprises a controllable current source when said sensing circuit is operating according to a drain-side sensing arrangement.
26. The method according to claim 19 , further comprising a sense current measurement circuit adapted to induce within a constituent branch a current whose amplitude is directly related the NVM cell current.
27. The method according to claim 26 , wherein said sense current measurement circuit comprises two mirroring circuit branches, each of which is coupled in a current mirroring arrangement with a corresponding branch of said sense-side-line conditioning circuit segment.