System and method for configuring a display pipeline
View Patent ↗Systems and methods are disclosed for video processing modules. More specifically a network is disclosed for processing data. The network comprises a register DMA controller adapted to support register access and at least one node adapted to the data. At least one link communicates with the node, and is adapted to transmit data and at least one network module communicates with at least the link, and is adapted to route data to at least the link.
1. A system for processing data, comprising:
a flow control module configured to control a rate of data flow in display pipelines; and
at least one system time reference recovery device configured to determine a timing reference of at least one input data stream;
wherein the flow control module is operable to enable different data flow rates for different display pipelines corresponding to a timing reference determined for each of the at least one input data stream.
2. The system of claim 1 , further comprising multiple nodes configurable to form the different display pipelines by varying respective positions of the multiple nodes within the different display pipelines.
3. The system of claim 1 , wherein a particular node is assigned a starting position within a first display pipeline and is assigned a non-starting position within a second display pipeline, wherein the different display pipelines comprise the first display pipeline and the second display pipeline.
4. The system of claim 1 , further comprising a control register of the flow control module that is operable to activate the flow control module by writing a control value to the control register.
5. The system of claim 1 , further comprising a frame buffer that is operable to capture an output of a first display pipeline, wherein the different display pipelines comprise the first display pipeline.
6. The system of claim 5 , wherein the frame buffer is operable to input content of the frame buffer to a second display pipeline, wherein the different display pipelines comprise the second display pipeline.
7. The system of claim 1 , further comprising a controller configured to form at least one display pipeline by dynamically selecting use of at least two selectable nodes from a plurality of selectable nodes and dynamically concatenating the selected at least two selectable nodes together.
8. The system of claim 7 , wherein the controller changes a functionality of the at least one display pipeline by dynamically concatenating more than two nodes together.
9. The system of claim 7 , wherein the controller is a register DMA controller configured to support register access.
10. The system of claim 9 , wherein the register DMA controller is further configured to provide at least one instruction to form the display pipeline.
11. The system of claim 9 , wherein the register DMA controller is further configured to obtain at least one instruction from a register update list.
12. A method comprising:
controlling a rate of data flow in display pipelines;
determining a timing reference of at least one input data stream; and
configuring multiple nodes from a first display pipeline to a second display pipeline by varying respective positions of the multiple nodes within the first and second display pipelines,
wherein different data flow rates are enabled for the first and second display pipelines corresponding to a timing reference determined for each of the at least one input data stream.
13. The method of claim 12 , further comprising forming the first and second display pipelines by varying respective positions of multiple nodes within the first and second display pipelines.
14. The method of claim 12 , wherein a particular node is assigned a starting position within the first display pipeline and is assigned a non-starting position within the second display pipeline.
15. The method of claim 12 , further comprising changing a flow rate associated with a particular display pipeline by writing a control value to a control register.
16. The method of claim 12 , further comprising capturing an output of the first display pipeline to a frame buffer and feeding a content of the frame buffer to the second display pipeline.
17. The method of claim 12 , wherein the second display pipeline is formed by dynamically selecting use of at least two selectable nodes from a plurality of selectable nodes and dynamically concatenating the selected at least two selectable nodes together.
18. The method of claim 17 , further comprising changing a functionality of the second display pipeline by dynamically concatenating more than two nodes together.
19. The method of claim 12 , further comprising:
obtaining at least one register update list from a main memory in response to receiving at least one trigger; and
writing a register update entry from the register update list to a register of a decoder, wherein the register update list stores instructions for configuring a display pipeline.
20. The method of claim 19 , wherein the register update list stores multiple instructions for updating multiple nodes of a display pipeline concurrently.