IP Library Granted Patent US 9,135,999
Granted Patent B2
US 9,135,999 · App. 14/077,474 · Granted Sep 15, 2015

Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding

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Quick Facts
Patent No.
US 9,135,999
App. No.
14/077,474
Granted
Sep 15, 2015
Kind
B2
Abstract

Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Claims (26)

1. A method for storing data in a multi-level cell flash memory device ( 120 ) having a plurality of cells, wherein each cell of said multi-level cell flash memory device is capable of storing a plurality of bits, wherein each of said plurality of bits is from a different page, said method comprising:

accumulating a plurality of said pages;

encoding said plurality of pages as a single block; and

storing said single block in said multi-level cell flash memory device, wherein at least one sector spans a plurality of pages.

2. The method of claim 1 , wherein said step of encoding said plurality of pages as a single block encodes said plurality of pages using a single code and a single code rate.

3. The method of claim 1 , wherein said step of encoding said plurality of pages as a single block encodes said plurality of pages using one or more of a plurality of codes and a plurality of code rates.

4. The method of claim 1 , wherein said step of encoding said plurality of pages as a single block encodes each of said plurality of pages using one or more of a unique code and a unique code rate for each of said plurality of pages.

5. The method of claim 1 , further comprising the step of partitioning said encoded single block into a plurality of pages and wherein said storing step comprises the step of storing each of said plurality of pages in said multi-level cell flash memory device.

6. The method of claim 1 , further comprising the step of decoding said stored single block.

7. The method of claim 1 , wherein said plurality of pages is a minimum data unit that may be used for reading and writing said multi-level cell flash memory device.

8. The method of claim 1 , wherein said step of accumulating said plurality of said pages further comprises the step of accumulating j by k sectors, where j is a number of pages per wordline in said multi-level cell flash memory device and k is a number of said sectors per page.

9. The method of claim 1 , wherein said multi-level cell flash memory device further comprises:

a plurality of wordlines each comprising a plurality of said pages, wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are substantially similar and a coded length of each of said plurality of pages are different.

10. The method of claim 1 , wherein said multi-level cell flash memory device further comprises:

a plurality of wordlines each comprising a plurality of said pages, wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are different and a coded length of each of said plurality of pages are substantially similar.

11. A multi-level cell flash memory device, comprising:

a plurality of cells, wherein each cell of said multi-level cell flash memory device is capable of storing a plurality of bits, wherein each of said plurality of bits is from a different page; and

a plurality of wordlines each comprising a plurality of said pages, wherein a plurality of said pages are encoded as a single block, wherein said single block is stored in said multi-level cell flash memory device, wherein at least one sector spans a plurality of pages.

12. The multi-level cell flash memory device of claim 11 , wherein said plurality of pages are encoded using a single code and a single code rate.

13. The multi-level cell flash memory device of claim 11 , wherein said plurality of pages are encoded using one or more of a plurality of codes and a plurality of code rates.

14. The multi-level cell flash memory device of claim 11 , wherein each of said plurality of pages are encoded using one or more of a unique code and a unique code rate for each of said plurality of pages.

15. The multi-level cell flash memory device of claim 11 , wherein said encoded single block is partitioned into a plurality of pages and wherein said storage comprises storing each of said plurality of pages in said multi-level cell flash memory device.

16. The multi-level cell flash memory device of claim 11 , wherein said plurality of pages is a minimum data unit that may be used for reading and writing said multi-level cell flash memory device.

17. The multi-level cell flash memory device of claim 11 , wherein j by k sectors are accumulated, where j is a number of pages per wordline in said multi-level cell flash memory device and k is a number of said sectors per page.

18. The multi-level cell flash memory device of claim 11 , wherein said plurality of wordlines each comprising a plurality of said pages, wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are substantially similar and a coded length of each of said plurality of pages are different.

19. The multi-level cell flash memory device of claim 11 , wherein said plurality of wordlines each comprising a plurality of said pages, wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are different and a coded length of each of said plurality of pages are substantially similar.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Mar 19, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 035226/0230 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →