IP Library Granted Patent US 9,058,879
Granted Patent B2
US 9,058,879 · App. 14/077,489 · Granted Jun 16, 2015

Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding

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Quick Facts
Patent No.
US 9,058,879
App. No.
14/077,489
Granted
Jun 16, 2015
Kind
B2
Abstract

Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Claims (32)

1. A method for storing data in a multi-level cell flash memory device having a plurality of cells, wherein each cell of said multi-level cell flash memory device is capable of storing a plurality of bits, wherein each of said plurality of bits is from a different page, said method comprising:

determining a page type of a current page to be written in said multi-level cell flash memory device;

determining at least one of a code and a code rate associated with said determined page type;

encoding said current page using said determined at least one code and code rate; and

storing said encoded current page in said multi-level cell flash memory device, wherein a first page type having a lower reliability than a second page type is encoded using one or more of a more powerful code and a lower code rate than said second page type.

2. The method of claim 1 , further comprising the steps of determining a number-of-sectors per page associated with said determined page type and accumulating said determined number-of-sectors prior to said step of encoding said current page.

3. The method of claim 1 , wherein each page in a wordline is encoded to a substantially similar length using a corresponding code rate.

4. The method of claim 1 , further comprising the steps of receiving a request to read at least one sector; identifying a page in said multi-level cell flash memory device having said requested sector; reading said identified page and decoding said read page using said at least one code and code rate associated with said identified page and obtaining said requested sector from said decoded page using a memory map.

5. The method of claim 1 , further comprising the step of decoding one or more pages using a multi-stage decoder comprising a plurality of decoding stages to decode a plurality of pages in a wordline.

6. The method of claim 5 , wherein a decoding stage for a first page provides a decision to a decoding stage for another page.

7. The method of claim 6 , wherein said decision is one or more of a hard decision and a soft decision.

8. The method of claim 1 , wherein a first page is decoded, and wherein said method further comprises the step of decoding at least one additional page if a decoding error for said first page is detected.

9. The method of claim 1 , wherein said multi-level cell flash memory device further comprises:

a plurality of wordlines each comprising a plurality of said pages, wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are substantially similar and a coded length of each of said plurality of pages are different.

10. The method of claim 1 , wherein said multi-level cell flash memory device further comprises:

a plurality of wordlines each comprising a plurality of said pages, wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are different and a coded length of each of said plurality of pages are substantially similar.

11. The method of claim 1 , wherein said multi-level cell flash memory device further comprises:

a plurality of cells, wherein each cell of said multi-level cell flash memory device is capable of storing a plurality of bits, wherein each of said plurality of bits is from a different page; and

a plurality of wordlines each comprising a plurality of said pages, wherein at least one sector spans said plurality of pages.

12. A multi-level cell flash memory device, comprising:

a plurality of cells, wherein each cell of said multi-level cell flash memory device is capable of storing a plurality of bits, wherein each of said plurality of bits is from a different page; and

a plurality of wordlines each comprising a plurality of said pages, wherein a current page is encoded using at least one code and code rate for a determined page type of said current page and wherein said encoded current page is stored in said multi-level cell flash memory device, wherein a first page type having a lower reliability than a second page type is encoded using one or more of a more powerful code and a lower code rate than said second page type.

13. The multi-level cell flash memory device of claim 12 , wherein a number-of-sectors per page associated with said determined page type is determined and wherein said determined number-of-sectors are accumulated prior to said encoding of said current page.

14. The multi-level cell flash memory device of claim 12 , wherein each page in a wordline is encoded to a substantially similar length using a corresponding code rate.

15. The multi-level cell flash memory device of claim 12 , wherein said multi-level cell flash memory device is further configured to receive a request to read at least one sector; identify a page in said multi-level cell flash memory device having said requested sector; read said identified page and decode said read page using said at least one code and code rate associated with said identified page and obtain said requested sector from said decoded page using a memory map.

16. The multi-level cell flash memory device of claim 12 , wherein one or more pages are decoded using a multi-stage decoder comprising a plurality of decoding stages to decode a plurality of pages in a wordline.

17. The multi-level cell flash memory device of claim 16 , wherein a decoding stage for a first page provides a decision to a decoding stage for another page.

18. The multi-level cell flash memory device of claim 17 , wherein said decision is one or more of a hard decision and a soft decision.

19. The multi-level cell flash memory device of claim 12 , wherein a first page is decoded, and wherein said multi-level cell flash memory device further comprises the step of decoding at least one additional page if a decoding error for said first page is detected.

20. The multi-level cell flash memory device of claim 12 , wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are substantially similar and a coded length of each of said plurality of pages are different.

21. The multi-level cell flash memory device of claim 12 , wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are different and a coded length of each of said plurality of pages are substantially similar.

22. The multi-level cell flash memory device of claim 12 , wherein each cell of said multi-level cell flash memory device is capable of storing a plurality of bits, wherein each of said plurality of bits is from a different page and wherein said plurality of wordlines each comprises a plurality of said pages, wherein at least one sector spans said plurality of pages.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Mar 19, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 035226/0230 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →