IP Library Granted Patent US 9,007,828
Granted Patent B2
US 9,007,828 · App. 14/077,519 · Granted Apr 14, 2015

Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding

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Quick Facts
Patent No.
US 9,007,828
App. No.
14/077,519
Granted
Apr 14, 2015
Kind
B2
Abstract

Methods and apparatus are provided for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding. A single sector can be stored across a plurality of pages in the flash memory device. Per-page control is provided of the number of sectors in each page, as well as the code and/or code rate used for encoding and decoding a given page, and the decoder or decoding algorithm used for decoding a given page. Multi-page and wordline level access schemes are also provided.

Claims (25)

1. A method for storing data in a multi-level cell flash memory device having a plurality of cells, wherein each cell of said multi-level cell flash memory device is capable of storing a plurality of bits, wherein each of said plurality of bits is from a different page, said method comprising:

determining a page type of a current page to be written in said multi-level cell flash memory device;

determining a number-of-sectors per page associated with said determined page type;

accumulating said determined number-of-sectors;

encoding said accumulated sectors; and

storing said accumulated sectors in said multi-level cell flash memory device, wherein said number-of-sectors per page is a non-integer number and at least one sector spans a plurality of pages.

2. The method of claim 1 , wherein at least one sector spans a plurality of pages and one or more of a multi-page access scheme and a wordline level access scheme are employed during said storing step.

3. The method of claim 1 , further comprising the step of buffering one or more fractional portions of a section for a subsequent page.

4. The method of claim 1 , wherein said step of storing said accumulated sectors employs one or more of a multi-page access scheme and a wordline level access scheme.

5. The method of claim 1 , further comprising the steps of receiving a request to read at least one sector; identifying one or more pages in said multi-level cell flash memory device having said requested sector; and reading said identified one or more pages using a page level, a multi-page and a wordline level access scheme.

6. The method of claim 5 , further comprising the steps of decoding said read identified one or more pages using at least one of a code and code rate associated with said identified one or more pages and obtaining said requested sector from said decoded one or more pages using a memory map.

7. The method of claim 1 , wherein said multi-level cell flash memory device further comprises:

a plurality of wordlines each comprising a plurality of said pages, wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are substantially similar and a coded length of each of said plurality of pages are different.

8. The method of claim 1 , wherein said multi-level cell flash memory device further comprises:

a plurality of wordlines each comprising a plurality of said pages, wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are different and a coded length of each of said plurality of pages are substantially similar.

9. A multi-level cell flash memory device, comprising:

a plurality of cells, wherein each cell of said multi-level cell flash memory device is capable of storing a plurality of bits, wherein each of said plurality of bits is from a different page; and

a plurality of wordlines each comprising a plurality of said pages, wherein a determined number-of-sectors per page associated with a determined page type of a current page is accumulated and wherein said accumulated sectors are encoded and stored in said multi-level cell flash memory device, wherein said number-of-sectors per page is a non-integer number and at least one sector spans a plurality of pages.

10. The multi-level cell flash memory device of claim 9 , wherein at least one sector spans a plurality of pages and one or more of a multi-page access scheme and a wordline level access scheme are employed during said storing step.

11. The multi-level cell flash memory device of claim 9 , wherein one or more fractional portions of a section are buffered for a subsequent page.

12. The multi-level cell flash memory device of claim 9 , wherein said storage of said accumulated sectors employs one or more of a multi-page access scheme and a wordline level access scheme.

13. The multi-level cell flash memory device of claim 9 , wherein said multi-level cell flash memory device is further configured to receive a request to read at least one sector; identify one or more pages in said multi-level cell flash memory device having said requested sector; and read said identified one or more pages using a page level, a multi-page and a wordline level access scheme.

14. The multi-level cell flash memory device of claim 13 , wherein said multi-level cell flash memory device is further configured to decode said read identified one or more pages using at least one of a code and code rate associated with said identified one or more pages and obtain said requested sector from said decoded one or more pages using a memory map.

15. The multi-level cell flash memory device of claim 9 , wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are substantially similar and a coded length of each of said plurality of pages are different.

16. The multi-level cell flash memory device of claim 9 , wherein each of said plurality of pages has an associated code rate such that an uncoded length of each of said plurality of pages are different and a coded length of each of said plurality of pages are substantially similar.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Mar 19, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 035226/0230 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →