SYSTEMS AND METHODS FOR ERASING CHARGE-TRAP FLASH MEMORY
FLASH memory device contains at least one memory stack. The stack of transistors includes a first (or source) selector transistor, a second (or drain) selector transistor, and a plurality memory cell transistors connected in series therebetween. During an erase operation, each of the first and second selector transistors has a bias applied that releases the select transistors from an electrically floating state together with biasing each of the memory cell transistors.
1 - 18 . (canceled)
19 . A method comprising:
performing an erase operation on a memory array comprising a first selector transistor and a first memory cell transistor coupled to the first selector transistor, and
the performing the erase operation comprising a sequence of first and second operations;
the first operation comprising:
applying a bias voltage to a gate of the first selector transistor to release the gate of the first selector transistor from an electrically floating condition, and
applying an erase voltage to a gate of the first memory cell transistor; and
the second operation comprising:
programming the first selector transistor.
20 . The method of claim 19 , wherein the gate the first selector transistor comprises a gate film trapping a charge.
21 . The method of claim 20 , wherein the gate film comprises a silicon nitride layer trapping a charge.
22 . The method of claim 19 , wherein the first selector transistor is coupled between a bit line and the first memory cell.
23 . The method of claim 19 , wherein the first selector transistor and the first memory cell are structured in a NAND type.
24 . The method of claim 19 , wherein the first selector transistor and the first memory cell transistor are substantially similar in gate structure.
25 . The method of claim 19 , wherein the gate of the first selector transistor comprises at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxi-nitride layer.
26 . The method of claim 19 , wherein the gate of the first selector transistor comprises a silicon oxide layer, a silicon nitride layer, and a silicon oxi-nitride layer that are stacked with one another.
27 . The method of claim 19 , wherein the performing the erase operation comprises verifying whether erasure of the first memory cell transistor has succeeded.
28 . The method of claim 19 , wherein the first operation comprises:
applying an additional erase voltage to a region in which the first selector transistor and the first memory cell transistor are formed.
29 . The method of claim 28 , wherein the region in which the first selector transistor and the first memory cell transistor are formed is a p-well.
30 . The method of claim 19 , wherein the first operation comprising:
applying an another additional erase voltage to a gate of a second memory cell transistor, the first memory cell transistor being coupled between the second memory cell transistor and the first selector transistor.
31 . The method of claim 30 , wherein the anther additional erase voltage is smaller than the erase voltage.
32 . The method of claim 19 , wherein the bias voltage are the erase voltage different in level from each other.
33 . The method of claim 32 , wherein the bias voltage is smaller than the erase voltage.