IP Library Granted Patent US 9,165,871
Granted Patent B2
US 9,165,871 · App. 14/078,727 · Granted Oct 20, 2015

Semiconductor unit and semiconductor device using the same

Inventor: Toshiyuki Miyanagi (Azumino, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L23/49575H01L23/3735H01L23/4334H01L23/492H01L23/49811H01L24/73H01L25/03H01L25/072H01L23/053H01L23/24H01L24/06H01L24/32H01L24/33H01L24/45H01L24/48H01L24/49H01L2224/04026H01L2224/04042H01L2224/0603H01L2224/06181H01L2224/291H01L2224/32225H01L2224/32245H01L2224/33181H01L2224/45014H01L2224/45124H01L2224/45147H01L2224/48137H01L2224/48139H01L2224/48227H01L2224/4903H01L2224/49111H01L2224/49175H01L2224/73215H01L2224/73265H01L2924/01047H01L2924/1033H01L2924/10253H01L2924/10272H01L2924/1203H01L2924/12032H01L2924/12041H01L2924/1305H01L2924/1306H01L2924/13055H01L2924/13062H01L2924/13091H01L2924/19107H01L2924/30107
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Quick Facts
Patent No.
US 9,165,871
App. No.
14/078,727
Granted
Oct 20, 2015
Kind
B2
Abstract

In some aspects of the invention, semiconductor unit can produce chips performing uniform parallel operation and a low-thermal-resistance. Aspects of the invention can include a plurality of small semiconductor chips of one and the same kind formed by use of an SiC substrate, which is a wide gap substrate are sandwiched between two conductive plates. In this manner, there can be provided a high-reliability semiconductor unit in which parallel operation of the semiconductor chips is uniformized so that breakdown caused by current concentration can be prevented.

Claims (31)

1. A semiconductor unit comprising:

a plurality of semiconductor chips connected in parallel, each of the semiconductor chips being an SiC switching device having one principal surface and an other principal surface, wherein a first main electrode is formed on the one principal surface while a second main electrode and a gate electrode are formed on the other principal surface;

a first common conductive plate having a first principal surface and a second principal surface, wherein the first main electrodes are joined to the first principal surface of the first common conductive plate;

a conductive block joined to the second main electrode;

a second common conductive plate having a first principal surface and a second principal surface, wherein the first principal surface of the second common conductive plate are connected to the conductive block;

an insulating resin packed in between the first principal surface of the first common conductive plate and the first principal surface of the second common conductive plate, with the second principal surface of the first common conductive plate and the second principal surface of the second common conductive plate being exposed; and

a third conductive plate electrically insulated from the second common conductive plate and passing through the second principal surface of the second common conductive plate, wherein the gate electrodes are connected to the third conductive plate.

2. The semiconductor unit according to claim 1 , wherein

the first common conductive plate is an insulating substrate including a rear surface and a front surface, wherein

a rear metal film is formed on the rear surface and a first conductive pattern is formed on the front surface,

the first main electrodes are joined to the first conductive pattern, and

the insulating substrate further comprises a connection conductor connecting the rear metal film to the first conductive pattern.

3. The semiconductor unit according to claim 2 ,

the insulating substrate further comprising a second conductive pattern formed on the front surface, wherein the gate electrodes are connected to the third conductive plate through the second conductive pattern.

4. A semiconductor unit having a plurality of semiconductor chips formed by use of a wide gap semiconductor substrate, and connected in parallel, the semiconductor unit comprising:

a plurality of semiconductor chips configured such that one principal surface of each of the semiconductor chips of the same type is joined onto a first principal surface of a first common conductive plate while each of a plurality of conductive blocks is joined to the other principal surface of each of the semiconductor chips; and

a first principal surface of a second common conductive plate joined onto the conductive blocks, and an insulating resin is packed in between the first principal surface of the first common conductive plate and the first principal surface of the second common conductive plate, while a second principal surface of the first common conductive plate and a second principal surface of the second common conductive plate are exposed,

each of the semiconductor chips is an SiC switching device in which a first main electrode is formed on the one principal surface while a second main electrode and a gate electrode are formed on the other principal surface, and which is provided with a third conductive plate electrically insulated from the second common conductive plate and passing through a second principal surface of the second common conductive plate;

the first main electrodes are joined to the first principal surface of the first common conductive plate while the second main electrodes are joined to the first principal surface of the second common conductive plate through the conductive blocks; and

the gate electrodes are connected to the third conductive plate.

5. A semiconductor device in which a first semiconductor unit and a second semiconductor unit are mounted and connected on a common insulating substrate, each of the first semiconductor unit and second semiconductor unit having a plurality of semiconductor chips formed by use of a wide gap semiconductor substrate, and connected in parallel, each of the first semiconductor unit and second semiconductor unit comprising:

a plurality of semiconductor chips configured such that one principal surface of each of the semiconductor chips of the same type is joined onto a first principal surface of a first common conductive plate while each of a plurality of conductive blocks is joined to the other principal surface of each of the semiconductor chips; and

a first principal surface of a second common conductive plate joined onto the conductive blocks, and an insulating resin is packed in between the first principal surface of the first common conductive plate and the first principal surface of the second common conductive plate, while a second principal surface of the first common conductive plate and a second principal surface of the second common conductive plate are exposed, wherein

the first semiconductor unit includes SiC-diode chips as the semiconductor chips and the second semiconductor unit includes SiC switching devices as the semiconductor chips, and

wherein,

in each of the SiC-diode chips, a cathode electrodes is formed on the one principal surface while an anode electrode is formed on the other principal surface;

the cathode electrodes are joined to the first principal surface of the first common conductive plate;

the anode electrodes are joined to the first principal surface of the second common conductive plate through the conductive blocks;

in each of the SiC switching devices, a first main electrode is formed on the one principal surface while a second main electrode and a gate electrode are formed on the other principal surface, and there is provided with a third conductive plate electrically insulated from the second common conductive plate and led out to a second principal surface side of the second common conductive plate;

the first main electrodes are joined to the first principal surface of the first common conductive plate while the second main electrodes are joined to the first principal surface of the second common conductive plate through the conductive blocks; and

the gate electrodes are joined to the third conductive plate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2013
From: MIYANAGI, TOSHIYUKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 031677/0994 →
Priority Claims (1)
JP 2011-134565 · Jun 16, 2011 · national
Continuity (2)
Continuation PCTJP2012064145 · May 31, 2012
Related Publication 20140061673A1 · Mar 6, 2014