IP Library Granted Patent US 9,263,291
Granted Patent B2
US 9,263,291 · App. 14/079,120 · Granted Feb 16, 2016

Method of manufacturing semiconductor device

Inventors: Koichi Toba (Kanagawa, JP); Hiraku Chakihara (Kanagawa, JP); Yoshiyuki Kawashima (Kanagawa, JP); Kentaro Saito (Kanagawa, JP); Takashi Hashimoto (Kanagawa, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H01L21/3105H01L21/823412H01L21/823468H01L27/0922H01L27/1157H01L27/11573H01L29/4234H01L29/42324H01L29/66825H01L29/66833
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Quick Facts
Patent No.
US 9,263,291
App. No.
14/079,120
Granted
Feb 16, 2016
Kind
B2
Abstract

To improve a semiconductor device having a nonvolatile memory. a first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.

Claims (27)

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) providing a semiconductor substrate having a first MISFET formed in a first region, and a second MISFET formed in a second region;

(b) forming a first insulating film over the first MISFET and the second MISFET;

(c) forming a second insulating film over the first insulating film;

(d) removing the second insulating film in the second region therefrom; and

(e) after the step (d), performing heat treatment to apply a stress to the first MISFET,

wherein a gate length of the first MISFET is smaller than a gate length of the second MISFET.

2. A method of manufacturing a semiconductor device according to claim 1 , further comprising the step of:

(f) after the step (e), removing the second insulating film.

3. A method of manufacturing a semiconductor device according to claim 2 ,

wherein, after the step (d), a thickness of the first insulating film in the second region is smaller than the thickness of the first insulating film in the first region.

4. A method of manufacturing a semiconductor device according to claim 3 , further comprising the step of:

(g) after the step (f), removing the first insulating film.

5. A method of manufacturing a semiconductor device according to claim 4 , further comprising the step of:

(h) after the step (g), forming a silicide film over each of source/drain regions of the first MISFET or the second MISFET formed in the semiconductor substrate formed of a silicon substrate.

6. A method of manufacturing a semiconductor device according to claim 1 ,

wherein the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film.

7. A method of manufacturing a semiconductor device according to claim 6 ,

wherein the step (d) is the step of etching the second insulating film in the second region using, as a mask, a photoresist film formed over the second insulating film in the first region.

8. A method of manufacturing a semiconductor device according to claim 6 ,

wherein the step (d) is the step of etching the second insulating film in the second region using, as a mask, a mask film made of a silicon oxide formed over the second insulating film in the first region.

9. A method of manufacturing a semiconductor device according to claim 3 , further comprising the steps of:

(g1) prior to the step (f), forming, over the first insulating film and the second insulating film, a third insulating film made of the same material as that of the first insulating film;

(g2) removing the third insulating film and the second insulating film in the first region therefrom; and

(g3) after the step (g2), removing the first insulating film and the third insulating film in the second region therefrom and removing the first insulating film in the first region therefrom.

10. A method of manufacturing a semiconductor device according to claim 2 , further comprising, between the steps (b) and (c), the step of:

removing a part of the first insulating film in the first region from a surface thereof such that a thickness of the first insulating film in the first region is smaller than the thickness of the first insulating film in the second region.

Assignments (2)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2013
From: TOBA, KOICHI; CHAKIHARA, HIRAKU; KAWASHIMA, YOSHIYUKI; SAITO, KENTARO; HASHIMOTO, TAKASHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 031594/0854 →
Priority Claims (1)
JP 2013-040061 · Feb 28, 2013 · national
Continuity (1)
Related Publication 20140242796A1 · Aug 28, 2014