Semiconductor memory device for storing multivalued data
View Patent ↗Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
1. A semiconductor memory device comprising:
first and second bit lines;
first, second and third word lines;
a plurality of memory cells including first, second, third and fourth memory cells, each memory cell capable of storing n bits of data (n is a natural number equal to or larger than two), the first memory cell connected to the first word line and coupled to the first bit line, the second memory cell connected to the second word line and coupled to the first bit line, a source of the second memory cell connected to a drain of the first memory cell, the third memory cell being adjacent to the second memory cell along the second word line, connected to the second word line and coupled to the second bit line, the fourth memory cell connected to the third word line and coupled to the first bit line, a source of the fourth memory cell connected to a drain of the second memory cell; and
a write circuit configured to write a first bit of data into the first memory cell, write a second bit of data into the second memory cell, write a third bit of data into the third memory cell and write a fourth bit of data into the fourth memory cell, before writing a fifth bit of data into the second memory cell without erasing the second bit of data in the second memory cell, wherein:
the write circuit is configured to write the second bit of data into the second memory cell by altering a threshold voltage of the second memory cell from a first voltage to a second voltage according to a first logical state of the second bit of data;
the write circuit is configured to write the fifth bit of data into the second memory cell by altering the threshold voltage of the second memory cell from the second voltage to a third voltage according to a first logical state of the fifth bit of data; and
the write circuit is configured to write the fifth bit of data into the second memory cell by altering the threshold voltage of the second memory cell from the second voltage to a fourth voltage higher than the third voltage according to a second logical state of the fifth bit of data.
2. The semiconductor memory device according to claim 1 , wherein the first logical state of the second bit of data is “0”.
3. The semiconductor memory device according to claim 1 , wherein:
the first logical state of the filth bit of data is “0”; and
the second logical state of the fifth bit of data is “1”.
4. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device is a NAND-type flash memory.
5. The semiconductor memory device according to claim 1 , wherein:
the write circuit is configured to write the first bit of data into the first memory cell before writing the second bit of data into the second memory cell;
the write circuit is configured to write the second bit of data into the second memory cell before writing the third bit of data into the third memory cell; and
the write circuit is configured to write the third bit of data into the third memory cell before writing the fourth bit of data into the fourth memory cell.
6. The semiconductor memory device according to claim 1 , the semiconductor memory device further comprising a fourth word line, wherein:
the memory cells further include fifth and sixth memory dells;
the fifth memory cell is adjacent to the fourth memory cell along the third word line, connected to the third word line and coupled to the second bit line, a source of the fifth memory cell connected to a drain of the third memory cell;
the sixth memory cell is connected to the fourth word line and coupled to the first bit line, a source of the sixth memory cell connected to a drain of the fourth memory cell; and
the write circuit is configured to write a sixth bit of data into the fifth memory cell and write a seventh bit of data into the sixth memory cell before writing an eighth bit of data into the fourth memory cell without erasing the fourth bit of data in the fourth memory cell.
7. The semiconductor memory device according to claim 6 , wherein the write circuit is configured to write the fifth bit of data into the second memory cell, write the eighth bit of data into the fourth memory cell and write a ninth bit of data into the third memory cell, before writing a tenth bit of data into the second memory cell.
8. The semiconductor memory device according to claim 7 , wherein:
the write circuit is configured to write the tenth bit of data into the second memory cell by altering the threshold voltage of the second memory cell from the third voltage to a fifth voltage according to a first logical state of the tenth bit of data;
the write circuit is configured to write the tenth bit of data into the second memory cell by altering the threshold voltage of the second memory cell from the third voltage to a sixth voltage according to a second logical state of the tenth bit of data;
the write circuit is configured to write the tenth bit of data into the second memory cell by altering the threshold voltage of the second memory cell from the fourth voltage to a seventh voltage according to a first logical state of the tenth bit of data; and
the write circuit is configured to write the tenth bit of data into the second memory cell by altering the threshold voltage of the second memory cell from the fourth voltage to an eighth voltage according to a second logical state of the tenth bit of data.
9. The semiconductor memory device according to claim 1 , wherein:
the write circuit includes a plurality of data storage circuits configured to store data to be written in the memory cells; and
the first and second bit lines are coupled to the same data storage circuit.
10. The semiconductor memory device according to claim 1 , wherein the write circuit is configured to write the second bit of data into the second memory cell by maintaining the threshold voltage of the second memory cell at the first voltage according to a second logical state of the second bit of data.
11. The semiconductor memory device according to claim 1 , the semiconductor memory device further comprising a plurality of flag cells, wherein the write circuit is configured to write flag information indicating that the fifth bit of data has been written into the second memory cell, into one of the flag cells selected concurrently with the second memory cell, when the write circuit writes the fifth bit of data into the second memory cell.