Granted Patent B2

US 9,098,330 · App. 14/079,308 · Granted Aug 4, 2015

Abstract

Claims (74)

1. A method for packet processing on a multi-core processor, the method comprising:

receiving a first packet at an input queue;

assigning a first processing phase identifier corresponding to a first processing phase of the first packet when the first packet has a plurality of processing phases;

assigning the first packet to a first processing core;

processing the first processing phase of the first packet on the first processing core;

assigning a second processing phase identifier corresponding to a second processing phase of the first packet when first packet has a second processing phase;

determining that the first processing core cannot process the second processing phase of the first packet because the first processing core enters a processing phase that locks the processing of the first packet;

storing the first packet in a de-schedule queue;

receiving a second packet at the input queue;

processing a processing phase of the second packet, wherein the processing of the processing phase of the second packet releases the lock on the processing of the first packet;

receiving one or more other packets at the input queue;

prioritizing the processing of the second phase of the first packet over the processing of the one or more other packets in the input queue, wherein the one or more other packets were received at a time after the first packet was received; and

processing the second processing phase of the first packet.

2. The method of claim 1 , further comprising:

assigning an incremental processing phase identifier corresponding to a next incremental processing phase of the first packet when the first packet has a next processing phase;

determining that the first processing core can process the next incremental processing phase of the first packet; and

processing the next incremental processing phase of the first packet on the first processing core.

3. The method of claim 1 , further comprising:

assigning an incremental processing phase identifier corresponding to a next incremental processing phase of the first packet when the first packet has a next processing phase;

determining that the first processing core cannot process the next incremental processing phase of the first packet because the firmware of the first processing core does not support the processing of the next incremental processing phase of the first packet;

redirecting the first packet to a second processing core; and

processing the next incremental processing phase of the first packet on the second processing core.

4. The method of claim 2 , further comprising:

assigning the first packet to a de-schedule queue when the first processing core cannot process the next incremental processing phase of the first packet because the first processing core enters a processing phase that locks the processing of the first packet;

storing the first packet in the de-schedule queue;

receiving a third packet;

processing a processing phase of the third packet, wherein the processing of the processing phase of the third packet releases the lock on the processing of the first packet;

prioritizing the processing of the next incremental phase of the first packet over the processing of packets received at a time after the first packet was received; and

processing the next incremental processing phase of the first packet.

5. The method of claim 1 , further comprising prior to processing the first processing phase of the first packet determining that the first processing core can process the first processing phase of the first packet.

6. The method of claim 5 , further comprising:

assigning an incremental processing phase identifier corresponding to a next incremental processing phase of the first packet when the first packet has a next processing phase;

determining that the first processing core can process the next incremental processing phase of the first packet; and

processing the next incremental processing phase of the first packet on the first processing core.

7. The method of claim 6 , further comprising:

redirecting the first packet to a second processing core when the first processing core cannot process the next incremental processing phase of the first packet because the firmware of the first processing core does not support the processing of the next incremental processing phase of the first packet; and

processing the next incremental processing phase of the first packet on the second processing core.

8. A non-transitory computer readable storage medium having embodied thereon a program executable to perform a method for packet processing on a multi-core processor, the method comprising:

receiving a first packet at an input queue;

assigning a first processing phase identifier corresponding to a first processing phase of the first packet when the first packet has a plurality of processing phases;

assigning the first packet to a first processing core;

processing the first processing phase of the first packet on the first processing core;

assigning a second processing phase identifier corresponding to a second processing phase of the first packet when first packet has a second processing phase;

determining that the first processing core cannot process the second processing phase of the first packet because the first processing core enters a processing phase that locks the processing of the first packet;

storing the first packet in a de-schedule queue;

receiving a second packet at the input queue;

processing a processing phase of the second packet, wherein the processing of the processing phase of the second packet releases the lock on the processing of the first packet;

receiving one or more other packets at the input queue;

prioritizing the processing of the second phase of the first packet over the processing of the one or more other packets in the input queue, wherein the one or more other packets were received at a time after the first packet was received; and

processing the second processing phase of the first packet.

9. The non-transitory computer readable storage medium of claim 8 , the program further executable to:

assign an incremental processing phase identifier corresponding to a next incremental processing phase of the first packet when the first packet has a next processing phase;

determine that the first processing core can process the next incremental processing phase of the first packet; and

process the next incremental processing phase of the first packet on the first processing core.

10. The non-transitory computer readable storage medium of claim 8 , the program further executable to:

assign an incremental processing phase identifier corresponding to a next incremental processing phase of the first packet when the first packet has a next processing phase;

determine that the first processing core cannot process the next incremental processing phase of the first packet because the firmware of the first processing core does not support the processing of the next incremental processing phase of the first packet;

redirect the first packet to a second processing core; and

process the next incremental processing phase of the first packet on the second processing core.

11. The non-transitory computer readable storage medium of claim 10 , the program further executable to:

assign the first packet to a de-schedule queue when the first processing core cannot process the next incremental processing phase of the first packet because the first processing core enters a processing phase that locks the processing of the first packet;

store the first packet in the de-schedule queue;

receive a third packet;

process a processing phase of the third packet, wherein the processing of the processing phase of the third packet releases the lock on the processing of the first packet;

prioritize the processing of the next incremental phase of the first packet over the processing of packets received at a time after the first packet was received; and

process the next incremental processing phase of the first packet.

12. The non-transitory computer readable storage medium of claim 8 , the program further executable to determine that the first processing core can process the first processing phase of the first packet prior to processing the first packet.

13. The non-transitory computer readable storage medium of claim 8 , the program further executable to:

assign an incremental processing phase identifier corresponding to a next incremental processing phase of the first packet when the first packet has a next processing phase;

determine that the first processing core can process the next incremental processing phase of the first packet; and

process the next incremental processing phase of the first packet on the first processing core.

14. The non-transitory computer readable storage medium of claim 13 , the program further executable to:

redirect the first packet to a second processing core when the first processing core cannot process the next incremental processing phase of the first packet because the firmware of the first processing core does not support the processing of the next incremental processing phase of the first packet; and

process the next incremental processing phase of the first packet on the second processing core.

Assignments (17)