IP Library Granted Patent US 9,122,577
Granted Patent B2
US 9,122,577 · App. 14/079,843 · Granted Sep 1, 2015

Systems and methods exchanging data between processors through concurrent shared memory

Inventors: Brent S. Baxter (Hillsboro, OR); Prashant Sethi (Folsom, CA); Clifford D. Hall (Orangeville, CA); William H. Clifford (Gig Harbor, WA)
Assignee: Intel Corporation
G06F12/0238G06F12/109
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Quick Facts
Patent No.
US 9,122,577
App. No.
14/079,843
Granted
Sep 1, 2015
Kind
B2
Abstract

A method and apparatus for matching parent processor address translations to media processors'address translations and providing concurrent memory access to a plurality of media processors through separate translation table information. In particular, a page directory for a given media application is copied to a media processor's page directory when the media application allocates memory that is to be shared by a media application running on the parent processor and media processors.

Claims (29)

1. An apparatus, comprising:

a central processing unit (CPU), the CPU to generate a pointer that is point to a virtual memory address;

at least one graphics processing unit (GPU), the at least one GPU coupled to the CPU, the at least one GPU to receive the pointer from the CPU; and

control logic to translate the virtual memory address to a physical memory address based on a page table mapping, the control logic to share the page table mapping with the at least one GPU, wherein based on the page table mapping, the at least one GPU is to access the physical memory address by use of the pointer that is to point to the virtual memory address.

2. The apparatus of claim 1 , further comprising a memory, the memory to include an addressable portion associated with the physical memory address.

3. The apparatus of claim 1 , wherein to share the page table mapping with the at least one GPU, the control logic is to copy at least one of a page directory, or at least one page table.

4. The apparatus of claim 1 , wherein, based on access of the physical memory address by use of the pointer, the at least one GPU is to process media information.

5. The apparatus of claim 4 , wherein the media information comprises at least one of video information or audio information.

6. A method, comprising:

generating, at a central processing unit (CPU), a pointer that points to a virtual memory address, wherein the virtual memory address is associated with a physical memory address according to a page table mapping;

receiving, at a graphics processor, the pointer from the CPU; and

accessing, at the graphics processor based on the page table mapping, the physical memory address using the pointer that points to the virtual memory address.

7. The method of claim 6 , wherein the page table mapping comprises a page directory and at least one page table, the method further comprising storing the page directory and the at least one page table in memory.

8. The method of claim 6 , further comprising based on accessing the physical memory address using the pointer, processing media information at the graphics processor.

9. The method of claim 8 , wherein the media information comprises at least one of video information or audio information.

10. At least one non-transitory machine readable medium having stored thereon one or more instructions that, when executed by a computing device, cause the computing device to:

generate, at a central processing unit (CPU), a pointer that points to a virtual memory address, wherein the virtual memory address is associated with a physical memory address according to a page table mapping;

receive, at a graphics processor, the pointer from the CPU; and

access, at the graphics processor based on the page table mapping, the physical memory address using the pointer that points to the virtual memory address.

11. The at least one non-transitory machine readable medium of claim 10 , wherein the page table mapping comprises a page directory and at least one page table, the at least one machine readable medium further having stored thereon one or more additional instructions that, when executed by the computing device, cause the computing device to store the page directory and the at least one page table in memory.

12. The at least one non-transitory machine readable medium of claim 10 , further having stored thereon one or more additional instructions that, when executed by the computing device, cause the computing device to process media information at the graphics processor based on accessing the physical memory address using the pointer.

13. The at least one non-transitory machine readable medium of claim 12 , wherein the media information comprises at least one of video information or audio information.

14. The apparatus of claim 1 , wherein the CPU and the at least one GPU are to share the page table mapping.

15. The apparatus of claim 1 , wherein the CPU is to access the physical memory address by use of the pointer based on the page table mapping.

16. The method of claim 6 , wherein the CPU and the graphics processor share the page table mapping.

17. The method of claim 6 , comprising:

accessing, at the CPU the physical memory address using the pointer and based on the page table mapping.

18. The at least one non-transitory machine readable medium of claim 10 , wherein the CPU and the graphics processor share the page table mapping.

19. The at least one non-transitory machine readable medium of claim 10 , having stored thereon one or more instructions that, when executed by a computing device, cause the computing device to: access, at the CPU the physical memory address by use of the pointer and based on the page table mapping.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2017
From: BAXTER, BRENT S.; SETHI, PRASHANT; HALL, CLIFFORD D.; CLIFFORD, WILLIAM H.
To: INTEL CORPORATION
Reel/Frame 041483/0336 →
Continuity (3)
Continuation 12349080 · Jan 6, 2009
Continuation 11022503 · Dec 22, 2004
Related Publication 20140075129A1 · Mar 13, 2014