Compensated temperature variable resistor
View Patent ↗A front-end circuit for measurement devices, for example oscilloscopes or digitizers, may implement DC gain compensation using a programmable variable resistance. A MOS transistor may be configured and operated as a linear resistor with the ability to self-calibrate quickly, while compensating for temperature variations. An integrated CMOS-based variable resistor may be thereby used for an analog adjustable attenuator. Master and slave CMOS transistors may be operated in linear mode, and temperature effects on the linear transistors may be compensated for by using an integral loop controller (current controller) configured around the master MOS transistor. Circuits implemented with the compensated variable resistance have a wide range of adjustment with a control voltage, and may be used in the front-end (circuits) of an oscilloscope or digitizer, or in any other circuit and/or instrumentation benefitting from an adjustable attenuator.
1. A resistance circuit comprising:
a first transistor device configured to operate in linear mode, and having an operative resistance value representative of a specified nominal resistance value;
a second transistor device having device characteristics commensurate with characteristics of the first transistor device, wherein the second transistor device is configured to operate in linear mode, and have an operative resistance value representative of the specified nominal resistance value; and
control circuitry configured to:
cause the operative resistance value of the second transistor device to return to the specified nominal resistance value when the operative resistance value of the second transistor device drifts away from the specified nominal resistance value due to changes in temperature; and
control the first transistor device by a control signal generated according to operation of the second transistor device, causing the operative resistance value of the first transistor device to return to the specified nominal resistance value when the operative resistance value of the first transistor device drifts away from the specified nominal resistance value due to changes in temperature.
2. The resistance circuit of claim 1 , wherein to cause the operative resistance value of the second transistor device to return to the specified nominal resistance value, the control circuit is configured to adjust a gate-source bias voltage of the second transistor device.
3. The resistance circuit of claim 1 , wherein the operative resistance value of the second transistor device is determined by a ratio of a reference voltage and a reference current applied at respective terminals of the second transistor device.
4. The resistance circuit of claim 1 , wherein during an equilibrium condition, a drop voltage produced across the second transistor device by a reference current equals a reference voltage applied to a channel terminal of the second transistor device.
5. The resistance circuit of claim 4 , wherein the control circuit comprises an integrator stage configured to enforce the equilibrium condition through negative feedback to the second transistor device.
6. The resistance circuit of claim 5 , wherein the integrator stage is configured to adjust a gate-source bias voltage of the second transistor device when an input error current into the integrator stage reaches a specified value.
7. The resistance circuit of claim 6 , wherein the specified value of the error current equals (V ref /R Vm )−I ref ;
wherein V ref is the value of the reference voltage;
wherein R Vm is the specified nominal resistance value; and
wherein I ref is the value of the reference current.
8. A method for compensating a DC (Direct Current) gain in a front-end circuit, the method comprising:
operating a first transistor device of the front-end circuit in linear mode, wherein the first transistor device has an operative resistance value representative of a specified nominal resistance value, and is configured in a feedback path of an inverting amplifier circuit of the front-end circuit;
operating a second transistor device of the front-end circuit in linear mode, wherein the second transistor device has an operative resistance value representative of the specified nominal resistance value;
causing the operative resistance value of the second transistor device to return to the specified nominal resistance value when the operative resistance value of the second transistor device drifts away from the specified nominal resistance value due to changes in temperature; and
causing the operative resistance value of the first transistor device to return to the specified nominal resistance value when the operative resistance value of the first transistor device drifts away from the specified nominal resistance value due to changes in temperature, comprising controlling the first transistor device by a control signal generated based on operation of the second transistor device.
9. The method of claim 8 , wherein said causing the operative resistance value of the second transistor device to return to the specified nominal resistance value comprises adjusting a gate-source bias voltage of the second transistor device.
10. The method of claim 8 , further comprising setting the operative resistance value of the second transistor device by applying a reference current and a reference voltage at respective terminals of the second transistor device, wherein the operative resistance value of the second transistor device is determined by a ratio of the reference voltage and the reference current
11. The method of claim 8 , further comprising:
producing, by a reference current, a drop voltage across the second transistor device; and
applying a reference voltage to a channel terminal of the second transistor device;
wherein during an equilibrium condition, the drop voltage equals the reference voltage.
12. The method of claim 11 , further comprising enforcing the equilibrium condition through an integrating, negative feedback path to the second transistor device.
13. The method of claim 12 , wherein said enforcing the equilibrium condition comprises adjusting a gate-source bias voltage of the second transistor device when an error current into the integrating, negative feedback path reaches a specified value.
14. A front-end circuit comprising:
an amplifier having a first input, a second input, and an output; and
a resistor network having a pair of terminals respectively coupled to the first input of the amplifier and the output of the amplifier, wherein the resistor network defines a DC (Direct Current) gain of the front-end circuit, wherein the resistor network comprises a first transistor device coupled to the output of the amplifier and configured to:
operate in linear mode, having an operative resistance value representative of a specified nominal resistance value; and
adjust its operative resistance value to return to the specified nominal resistance value responsive to a control signal, when the operative resistance value of the first transistor device drifts away from the specified nominal resistance value due to changes in temperature.
15. The front-end circuit of claim 14 , further comprising a capacitor network having three terminals respectively coupled to an input of the front-end circuit, the output of the amplifier, and the first input of the amplifier, wherein the capacitor network defines an AC (Alternating Current) gain of the front-end circuit.
16. The front-end circuit of claim 15 , wherein the capacitor network comprises:
a first capacitor coupled across the input of the front-end circuit and the first input of the amplifier; and
a second capacitor coupled across the first input of the amplifier and the output of the amplifier;
wherein the AC gain is determined by a ratio of the first capacitor and the second capacitor.
17. The front-end circuit of claim 14 , further comprising:
a second transistor device configured to operate in linear mode, having an operative resistance value representative of the specified nominal resistance value; and
an integral loop controller configured around the second transistor device, and further configured to;
adjust the operative resistance value of the second transistor device to return to the specified nominal resistance value when the operative resistance value of the first transistor device drifts away from the specified nominal resistance value due to changes in temperature; and
generate the control signal according to adjustments made to the operative resistance value of the second transistor device.
18. The front-end circuit of claim 17 , wherein in adjusting the operative resistance value of the second transistor device, the integral loop controller is configured to adjust a gate to source bias voltage of the second transistor device.
19. The front-end circuit of claim 17 , wherein the specified nominal resistance value is determined by a value of a current reference applied to the second transistor device, and a value of a reference voltage applied to the second transistor device.
20. The front-end circuit of claim 17 , wherein the integral loop controller is configured to adjust a value of the control signal when an input error current in the integral loop controller reaches a specified value.