Programming method for NAND flash memory device to reduce electrons in channels

1. A programming method for use with a NAND flash memory device comprising a memory cell array formed on a P-well of a semiconductor substrate, the memory cell array including a plurality of cell strings connected to word lines and being divided into a plurality of blocks, each block corresponding to respective word lines selected from the word lines, the programming method including the steps of:

reducing channel electrons in the cell strings; and

applying a program voltage to at least one selected word line while applying one or several pass voltages Vpass in a range between OV and the program voltage, to deselected word lines after the step of reducing.

2. The method as claimed in claim 1 ,

wherein the step of reducing includes a step of negatively biasing the word lines against the P-well.

3. The method as claimed in claim 2 ,

wherein the step of negatively biasing includes a step of applying a negative voltage to the word lines with the P-well grounded.

4. The method as claimed in claim 2 ,

wherein the word line which is negatively biased is only one word line connected to a memory cell to be programmed.

5. The method as claimed in claim 2 ,

wherein the step of negatively biasing includes a step of applying a negative voltage to a plurality of word lines in a memory string, which include one word line connected to a memory cell to be programmed.

6. The method as claimed in claim 2 ,

wherein the step of negatively biasing includes a step of applying a negative voltage to all the word lines in a selected block including a memory cell to be programmed.

7. The method as claimed in claim 2 ,

wherein the step of negatively biasing includes a step of applying a negative voltage to all the word lines in a plurality of selected blocks, one selected block including a memory cell to be programmed.

8. The method as claimed in claim 1 , further for use with a plurality of bit lines,

wherein each cell string is connected to each bit line, and

wherein the method further includes the steps of:

applying a voltage corresponding to the program voltage to a bit line connected to a memory string to be programmed before the step of reducing the channel electrons; and

applying a voltage corresponding to a program inhibit voltage to a bit line connected to a memory string to be unprogrammed before the step of reducing the channel electrons.

9. The method as claimed in claim 1 , further for use with a plurality of bit lines,

wherein each cell string is connected to each bit line, and

wherein the method further includes the steps of:

applying a voltage corresponding to a program inhibit voltage to the bit lines before the step of reducing the channel electrons; and

applying a voltage corresponding to the program voltage to a bit line connected to a memory string to be programmed at start of programming.

10. The method as claimed in claim 1 ,

wherein the step of reducing includes a step of positively biasing the P-well against the word lines in a memory string.

11. The method as claimed in claim 10 ,

wherein the step of positively biasing includes a step of applying a positive voltage to the P-well with the word lines in the memory string grounded.

12. The method as claimed in claim 10 ,

wherein the step of positively biasing includes a step of applying a positive voltage to the P-well while applying a negative voltage to the word lines in the memory string.

13. The method as claimed in claim 10 , further including a step of grounding the P-well upon applying the program voltage.

14. The method as claimed in claim 10 ,

wherein the step of positively biasing the P-well against the word lines includes a step of applying a negative voltage to only one word line connected to a memory cell to be programmed.

15. The method as claimed in claim 10 ,

wherein the step of positively biasing includes a step of applying a negative voltage to a plurality of word lines in the memory string, which include one word line connected to a memory cell to be programmed.

16. The method as claimed in claim 10 ,

wherein the step of positively biasing includes a step of applying a negative voltage to a plurality of word lines in the memory string, which include all the word lines in a selected block including a memory cell to be programmed.

17. The method as claimed in claim 10 ,

wherein the step of positively biasing includes a step of applying a negative voltage to a plurality of selected word lines, which include all the word lines in a plurality of selected blocks, one selected block including a memory cell to be programmed.

18. The method as claimed in claim 10 , further for use with a plurality of bit lines, and further including a step of setting the bit lines to a floating state upon positively biasing the P-well.

19. The method as claimed in claim 18 , further including the steps of:

applying a voltage corresponding to the program voltage to a bit line including a memory cell to be programmed before the step of positively biasing the P-well; and

applying a voltage corresponding to a program inhibit voltage to the bit lines except for the bit line including the memory cell to be programmed before the step of positively biasing the P-well.

20. The method as claimed in claim 18 , further including the steps of:

applying a voltage corresponding to the program voltage to a bit line including a memory cell to be programmed after the step of positively biasing the P-well; and

applying a voltage corresponding to a program inhibit voltage to the bit lines except for the bit line including the memory cell to be programmed after the step of positively biasing the P-well.

21. The method as claimed in claim 18 , further including the steps of:

applying a voltage corresponding to a program inhibit voltage to the bit lines before the step of positively biasing the P-well; and

applying a voltage corresponding to the program voltage to the bit lines including the memory cell to be programmed upon programming the memory cell.

22. The method as claimed in claim 2 ,

wherein the step of negatively biasing the word lines against the P-well includes a step of changing a relative voltage to be biased to the selected word lines, against the P-well, in an order of a negative voltage before a first period, OV in the first period, the pass voltage Vpass in a second period, and the program voltage or the pass voltage Vpass in a third period.

23. The method as claimed in claim 2 ,

wherein the step of negatively biasing the word lines against the P-well includes a step of changing a relative voltage to be biased to the selected word lines, against the P-well, in an order of OV before a first period, a negative voltage in the first period, the pass voltage Vpass in a second period, and the program voltage or the pass voltage Vpass in a third period.

24. The method as claimed in claim 2 ,

wherein the step of negatively biasing the word lines against the P-well includes a step of changing a relative voltage to be biased to the selected word lines, against the P-well, in an order of a pre-charge voltage before a first period, a negative voltage in the first period, the pass voltage Vpass in a second period, and the program voltage or the pass voltage Vpass in a third period.

25. The method as claimed in claim 2 ,

wherein the step of negatively biasing the word lines against the P-well includes a step of changing a relative voltage to be biased to the selected word lines, against the P-well, in an order of a negative voltage, and then, the program voltage or the pass voltage Vpass.

26. A NAND flash memory device comprising:

a memory cell array formed on a P-well of a semiconductor substrate, the memory cell array including a plurality of cell strings connected to word lines and being divided into a plurality of blocks, each block corresponding to respective word lines selected from the word lines;

means for applying a program voltage to at least one selected word line in a selected block while applying a pass voltage Vpass to deselected word lines; and

means for reducing channel electrons in the cell strings before applying the program voltage.

27. The NAND flash memory device as claimed in claim 26 ,

wherein the means for reducing the channel electrons applies a negative voltage to the word lines in the selected block.

28. The NAND flash memory device as claimed in claim 26 ,

wherein the means for applying the program voltage includes a row decoder,

wherein the row decoder comprises:

a block decoder for decoding an address signal to a select signal for selecting a block;

a level shifter for converting a predetermined voltage into a gate drive voltage in response to the select signal; and

a word line driver for transferring a global word line voltage to the word lines,

wherein each of the level shifter and the word line driver includes N-channel transistors which are formed in a Triple-well of the semiconductor substrate, and

wherein the row decoder generates a negative voltage for reducing the channel electrons.

29. The NAND flash memory device as claimed in claim 28 ,

wherein the row decoder changes the negative voltage to OV after reducing the channel electrons.

30. The NAND flash memory device as claimed in claim 28 ,

wherein the row decoder generates a high voltage higher than the negative voltage, and

wherein the high voltage at least upon reducing the channel electrons is set to be lower than a voltage obtained by an equation of the high voltage upon programming minus absolute value of the negative voltage.

31. The NAND flash memory device as claimed in claim 26 ,

wherein the means for applying the program voltage includes a row decoder,

wherein the row decoder comprises:

a block decoder for decoding an address signal to a select signal for selecting a block;

a level shifter for converting a predetermined voltage into a gate drive voltage in response to the select signal; and

a word line driver for transferring a global word line voltage to the word lines,

wherein the level shifter includes P-channel transistors.

32. The NAND flash memory device as claimed in claim 26 ,

wherein the means for reducing channel electrons applies a positive voltage to the P-well of the semiconductor substrate.

33. The NAND flash memory device as claimed in claim 32 ,

wherein the means for reducing channel electrons inputs the positive voltage from an external circuit, and applies the positive voltage to the P-well of the semiconductor substrate.

34. A NAND flash memory device comprising:

a memory cell array formed on a P-well of a semiconductor substrate, the memory cell array including a plurality of cell strings connected to word lines and being divided into a plurality of blocks, each block corresponding to respective word lines selected from the word lines, each block being divided into a plurality of pages each page located along each word line, each page being divided into a plurality of sector corresponding to a predetermined number of memory cells,

reducing means for reducing channel electrons in the cell strings; and

programming means for programming memory cells in a unit of one sector selected from the sectors located within one page after reducing channel electrons;

wherein, when the programming means updates data stored in a first sector of a first page of a first block, the programming means randomly programs updated data onto one or more of the following:

(a) a second sector of the first page of the first block;

(b) a sector of a second page of the first block; and

(c) a sector of a page of a second block.