Nonvolatile memory element and method for manufacturing the same
View Patent ↗A nonvolatile memory element includes a first and a second electrode layers, and a variable resistance layer provided between the first and the second electrode layers and having a resistance value reversibly changing according to application of an electrical pulse, wherein the variable resistance layer includes a first variable resistance layer contacting the first electrode layer and comprising an oxygen-deficient first metal oxide, and a second variable resistance layer contacting the first variable resistance layer and comprising a second metal oxide having a smaller oxygen deficiency than the first metal oxide, and including host layers and an inserted layer between each of adjacent pairs of the host layers, wherein the second metal oxide of the inserted layer has a larger oxygen deficiency than the second metal oxide of the host layer, and the first metal oxide has a larger oxygen deficiency than the second metal oxide of the host layer.
1. A method for manufacturing a nonvolatile memory element, the method comprising:
forming a first electrode layer above a substrate;
forming, above the first electrode layer, a first variable resistance layer comprising an oxygen-deficient first metal oxide;
forming, above the first variable resistance layer, a second variable resistance layer which comprises a second metal oxide, and includes a plurality of host layers and an inserted layer provided between each of adjacent pairs of the host layers, the second metal oxide having a degree of oxygen deficiency smaller than a degree of oxygen deficiency of the first metal oxide; and
forming a second electrode layer on the second variable resistance layer,
wherein in the forming of a second variable resistance layer,
the host layer is formed above the first variable resistance layer, the host layer comprising the second metal oxide having a degree of oxygen deficiency smaller than the degree of oxygen deficiency of the first metal oxide,
the inserted layer is formed above the host layer, the inserted layer comprising the second metal oxide having a degree of oxygen deficiency larger than a degree of oxygen deficiency of the host layer, and
another host layer is formed above the inserted layer, after the host layer and the inserted layer are formed at least once in this order, the another host layer comprising the second metal oxide having a degree of oxygen deficiency smaller than a degree of oxygen deficiency of the inserted layer.
2. The method for manufacturing a nonvolatile memory element according to claim 1 , further comprising:
forming, above the second resistance layer, a third variable resistance layer comprising a third metal oxide having a stoichiometric composition; and
forming the second electrode layer above the third variable resistance layer.
3. The method for manufacturing a nonvolatile memory element according to claim 1 ,
wherein in the forming of a host layer, reactive sputtering using a metal target is performed in an atmosphere having a flow rate of oxygen gas that is a first rate, and
in the forming of an inserted layer, reactive sputtering using the metal target is performed in an atmosphere having a flow rate of oxygen gas that is a second rate smaller than the first rate.
4. The method for manufacturing a nonvolatile memory element according to claim 1 ,
wherein in the forming of a second variable resistance layer, the second variable resistance layer is formed above the substrate consecutively after a variable resistance layer is formed above a dummy substrate different from the substrate prior to the formation of the second variable resistance layer above the substrate.
5. The method for manufacturing a nonvolatile memory element according to claim 1 , further comprising
forming a non-ohmic element which includes a first conductive layer in contact with the second electrode layer, a second conductive layer, and a semiconductor layer or an insulating layer which is provided between the first conductive layer and the second conductive layer.