IP Library Granted Patent US 9,508,774
Granted Patent B2
US 9,508,774 · App. 14/082,303 · Granted Nov 29, 2016

Semiconductor device and manufacturing method of the same

Inventor: Koji Iizuka (Kanagawa, JP)
Assignee: Renesas Electronics Corporation
H01L27/14685H01L27/14601H01L27/14636H01L27/14683H01L27/146H01L27/14621H01L27/14643
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,508,774
App. No.
14/082,303
Granted
Nov 29, 2016
Kind
B2
Abstract

There are provided a highly reliable semiconductor device capable of suppressing occurrence of cracks as well as securing flatness and a manufacturing method therefor. The semiconductor device includes: a semiconductor substrate; an element region; and a non-element region. The non-element region includes: a top-layer metal wiring in a top layer of metal wirings formed in the non-element region; a flattening film covering an upper surface of the top-layer metal wiring; and a protecting film formed over the flattening film. A removed part where the protecting film is removed is formed in at least part of the non-element region.

Claims (42)

1. A semiconductor device, comprising:

a semiconductor substrate having a main surface;

an element region where photodetectors are formed in the semiconductor substrate; and

a non-element region formed outside the element region over the main surface,

the non-element region including:

a top-layer metal wiring in a top layer of metal wirings formed in the non-element region;

a flattening film covering an upper surface of the top-layer metal wiring; and

a protecting film formed over the flattening film;

a removed part formed by removing the protecting film in at least part of the non-element region; and

a first slot formed by removing only a portion of the flattening film exposed by the removed part, the first slot reaching at least a depth of the upper surface of the top-layer metal wiring from the upper surface of the flattening film.

2. A semiconductor device according to claim 1 , wherein the removed part includes a level difference where a bottom of the level difference is an upper surface of the flattening film located above an upper surface of the top-layer metal wiring on a side opposite to the semiconductor substrate.

3. A semiconductor device according to claim 1 , wherein the top-layer metal wiring surrounds the element region in a plan view.

4. A semiconductor device according to claim 2 , wherein the first slot reaches at least the depth of the upper surface of the top-layer metal wiring from the upper surface of the flattening film in part of a region of the level difference.

5. A semiconductor device according to claim 4 , wherein the first slot is formed immediately above the top-layer metal wiring.

6. A semiconductor device according to claim 4 , wherein the first slot is formed outside the top-layer metal wiring in a plan view.

7. A semiconductor device according to claim 1 ,

wherein the removed part includes a first slot reaching at least the depth of the upper surface of the top-layer metal wiring from an upper surface of the protecting film, and

wherein the protecting film extends to an end portion of the main surface.

8. A semiconductor device according to claim 7 , wherein the first slot is formed immediately above the top-layer metal wiring.

9. A semiconductor device according to claim 7 , wherein the first slot is formed outside the top-layer metal wiring over the main surface.

10. A semiconductor device according to claim 7 ,

wherein the first slot extends, in a plan view, along an edge portion of the element region, and

wherein the removed part further includes a second slot, outside the first slot, in a plan view, extending in a direction intersecting with the first slot.

11. A semiconductor device according to claim 7 , wherein a film thickness of the protecting film is 0.3 μm or smaller.

12. A method for manufacturing a semiconductor device, comprising

providing a semiconductor substrate having a main surface;

forming an element region where photodetecors are formed in the semiconductor substrate and a non-element region outside the element region over the main surface;

forming a top-layer metal wiring in a top layer of metal wirings formed in the non-element region, a flattening film covering an upper surface of the top-layer metal wiring, and a protecting film formed over the flattening film in the non-element region;

forming a removed part where the protecting film is removed such that the flattening film remains over a surface of the top-layer metal wiring in the non-element region; and

forming a first slot by removing only a portion of the flattening film exposed by the removed part, the first slot reaching at least a depth of the upper surface of the top-layer metal wiring from the upper surface of the flattening film.

13. A method for manufacturing a semiconductor device according to claim 12 , wherein the removed part includes a level difference where a bottom of the level difference is an upper surface of the flattening film located above an upper surface of the top-layer metal wiring on a side opposite to the semiconductor substrate.

14. A method for manufacturing a semiconductor device according to claim 13 , wherein the first slot is formed in part of the region of the level difference.

15. A method for manufacturing a semiconductor device according to claim 14 , wherein the first slot is formed immediately above the top-layer metal wiring.

16. A method for manufacturing a semiconductor device according to claim 14 , wherein the first slot is formed, in a plan view, outside the top-layer metal wiring.

17. A method for manufacturing a semiconductor device according to claim 12 ,

wherein the removed part includes a first slot reaching at least the depth of the upper surface of the top-layer metal wiring from an upper surface of the protecting film, and

wherein the protecting film extends to an end portion of the main surface.

18. A method for manufacturing a semiconductor device according to claim 17 , wherein the first slot is formed immediately above the top-layer metal wiring.

19. A method for manufacturing a semiconductor device according to claim 17 , wherein the first slot is formed outside the top-layer metal wiring over the main surface.

20. A method for manufacturing a semiconductor device according to claim 17 ,

wherein the first slot extends, in a plan view, along an edge portion of the element region, and

wherein, in the step of forming the removed part, a second slot is formed outside the first slot, in a plan view, extending in a direction intersecting with the first slot.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044533/0739 →
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2013
From: IIZUKA, KOJI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 031619/0344 →
Priority Claims (1)
JP 2012-262828 · Nov 30, 2012 · national
Continuity (1)
Related Publication 20140151838A1 · Jun 5, 2014