Imaging device

1. An imaging device, comprising:

an array of pixels arranged in rows and columns comprising:

a signal device configured to enable any given pixel within one of a row and column; and

an integration period selection circuit associated with each said one of row and column;

wherein said integration period selection circuit is configured to receive a signal via a readout line from an enabled pixel and initiate a selected integration period for said enabled pixel;

wherein the readout line is configured for transmitting pixel sample data to the integration selection circuit to initiate the selected integration period and the readout line is futher configured to transmit pixel readout data associated with each said one of row and column; and

wherein an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence, and said image acquisition sequence being a period for acquiring a single frame.

2. An imaging device as in claim 1 wherein a transistor in a pixel responds to concurrence of a signal which enables said pixel in said one of row and column and the signal to select the integration period for the enabled pixel.

3. An imaging device as in claim 1 wherein an integration period for each pixel within said array of pixels is independent of neighboring pixels determined within a corresponding image acquisition sequence.

4. An imaging device as in claim 1 wherein a start of an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

5. An imaging device as in claim 1 wherein pixel structure is based on one of the 3T pixel design and a 4T pixel design.

6. An imaging device as in claim 1 wherein the integration period selection circuit comprises logic configured to determine whether a conditional reset or an unconditional reset is applied to any given pixel within said one of the row and column.

7. An imaging device, comprising:

columns of pixels, each one of a row and a column comprising:

a circuit configured to receive an input from any selected pixel from an associated one of said row and said column;

wherein said circuit is further configured to automatically select an integration period for a selected pixel and to output a signal to said selected pixel to initiate a selected integration period;

wherein a first transistor within each pixel is configured to receive a first signal indicating when the pixel within one of said row and said column is currently selected and a second signal from an associated circuit indicating a selected integration period for said selected pixel; and

wherein said transistor outputs a signal which at least in part controls initiation of the selected integration period for said selected pixel, wherein an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence, and said image acquisition sequence being a period for acquiring a single frame.

8. An imaging device as in claim 7 wherein said first transistor is coupled to a transfer gate transistor which initiates transfer of charge from a light induced charge accumulating site within said selected pixel to a charge storage site within said selected pixel, this action being used at least in part to initiate a selectable integration period chosen for the pixel.

9. An imaging device as in claim 7 wherein said first transistor is coupled to a reset transistor which resets said selected pixel to perform tasks which include initiation of a selectable integration period for said selected pixel.

10. An imaging device as in claim 7 wherein pixel structure is based on one of a 3T pixel design and a 4T pixel design.

11. An imaging device, comprising:

at least a substantial subset of one of rows and columns of pixels, each said one of row and column of pixels in said subset comprising:

a circuit configured to receive an input from a selected pixel from an associated one of said row and said column

wherein said circuit is further configured to automatically select an integration period for said selected pixel and to output a signal to said selected pixel to initiate a selected integration period, wherein an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence, and said image acquisition sequence being a period for acquiring a single frame; and

wherein said selected integration period is selected from a discret set of available integration periods.

12. An imaging device as in claim 11 wherein said input to said circuit from said selected pixel is an analog input.

13. An imaging device as in claim 11 , each said circuit comprising a memory associated with said selected pixel to record an indication of said selected integration period for said selected pixel.

14. An imaging device as in claim 13 wherein settings in said memory are used at least in part, to select an integration period for said selected pixel.

15. An imaging device as in claim 11 wherein the result of a comparison is used in part to select an integration period for said selected pixel.

16. An imaging device as in claim 11 wherein said circuit is configured to receive an input from a selected pixel in an associated one of said row and said column, to select an integration period for said selected pixel and to output a signal to said selected pixel to initiate said selected integration period within a single task.

17. An imaging device as in claim 11 wherein conditional selection and initiation of integration periods occur substantially in parallel for multiple one of rows and columns, each comprising an associated column circuit.

18. An imaging device as in claim 11 wherein a first transistor within each pixel is configured to receive a first signal indicating when the pixel within one of said row and said column is currently selected and a second signal from an associated circuit indicating a selected integration period for said selected pixel, wherein said transistor outputs a signal which at least in part controls initiation of said selected integration period for said selected pixel.

19. An imaging device as in claim 11 wherein pixel values are digitized only once per image acquisition sequence.

20. An imaging device as in claim 11 wherein pixel structure is based on one of a 3T pixel design and a 4T pixel design.