Semiconductor device and fabricating method thereof

1. A semiconductor device, comprising:

a substrate;

a pad on the substrate;

a conductive layer electrically coupled to the pad at one end;

a metal bump having a top surface and a sidewall, wherein the metal bump is configured to receive a solder bump, wherein the metal bump is electrically coupled to the pad via the conductive layer;

a dielectric layer surrounding the sidewall of the metal bump and having a top surface, and the top surface of the metal bump entirely protruding the top surface of the dielectric layer; and

a polymer layer on the top surface of the dielectric layer, wherein an entire top surface of the polymer layer is a continuous curved surface, and an average thickness of the polymer layer is greater than a thickness of the dielectric layer, and wherein the polymer layer has a CTE greater than a CTE of the dielectric layer, and the polymer layer is spaced from both the sidewall of the metal bump and a nearest outer edge of the solder bump with a gap.

2. The semiconductor device of claim 1 , wherein the sidewall of the metal bump is tapered.

3. The semiconductor device of claim 1 , wherein the metal bump includes a bottom surface contacting with the conductive layer.

4. The semiconductor device of claim 1 , wherein the metal bump has a thickness between about 8.0 μm and about 12.0 μm.

5. The semiconductor device of claim 1 , wherein the metal bump is leveled to be above the top surface of the dielectric layer with a gap between about 1.0 μm and about 3.0 μm.

6. The semiconductor device of claim 1 , wherein the metal bump includes Pb, Sn, Ni or Cu.

7. A semiconductor device, comprising:

an oval-shaped pad on a substrate; wherein the oval-shaped pad includes a major axis corresponding to a largest distance of the oval-shaped pad, and the major axis is toward a geometric center of the substrate;

a dielectric layer surrounding the oval-shaped pad and having a top surface, and

a polymer layer covering the dielectric layer and surrounding the oval-shaped pad;

wherein an entire top surface of the polymer layer is a continuous curved surface, an average thickness of the polymer layer is greater than a thickness of the dielectric layer, and the oval-shaped pad has a top surface entirely protruding the top surface of the dielectric layer, and the top surface of the oval-shaped pad is configured to be in direct contact with a solder bump, and

wherein a portion of the polymer layer over a singulation line is removed from the dielectric layer and thereby exposing the dielectric layer at the singulation line, and the polymer layer is spaced from both a sidewall of the oval-shaped pad and a nearest outer edge of the solder bump with a gap.

8. The semiconductor device of claim 7 , wherein the oval-shaped pad is on a peripheral region of the substrate.

9. The semiconductor device of claim 7 , further comprising a plurality of oval-shaped pads disposed symmetrically to the geometric center of the substrate.

10. The semiconductor device of claim 9 , further comprising a non oval-shaped pad, wherein the oval-shaped pad has a same top surface area as the non oval-shaped pad.

11. A method for fabricating a semiconductor device, comprising:

providing a substrate;

disposing a pad on the substrate;

forming a conductive layer electrically coupled to the pad;

disposing a dielectric layer over the conductive layer;

forming an opening in the dielectric layer thereby exposing a portion of the conductive layer;

filling a conductive material in the opening to overflow a top surface of the dielectric layer;

forming a substantially filled conductive pad with a top surface entirely protruding the top surface of the dielectric layer;

planting a solder bump atop the substantially filled conductive pad;

forming a polymer layer above the dielectric layer, wherein an entire top surface of the polymer layer is a continuous curved surface, and an average thickness of the polymer layer is greater than a thickness of the dielectric layer; and

spacing the polymer layer from both the substantially filed conductive pad and a nearest outer edge of the solder bump with a gap.

12. The method of claim 11 , further comprising surrounding a sidewall of the substantially filled conductive pad with the dielectric layer.

13. The method of claim 11 , further comprising forming a top surface at a top of the substantially filled conductive pad, wherein the top surface is over the top surface of the dielectric layer.

14. The method of claim 11 , further comprising surrounding a sidewall of the solder bump with the polymer layer.