IP Library Granted Patent US 8,928,004
Granted Patent B2
US 8,928,004 · App. 14/085,523 · Granted Jan 6, 2015

Structure for growth of nitride semiconductor layer, stacked structure, nitride-based semiconductor element, light source, and manufacturing method for same

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Quick Facts
Patent No.
US 8,928,004
App. No.
14/085,523
Granted
Jan 6, 2015
Kind
B2
Abstract

A structure for growth of a nitride semiconductor layer which is disclosed in this application includes: a sapphire substrate of which growing plane is an m-plane; and a plurality of ridge-shaped nitride semiconductor layers provided on the growing plane of the sapphire substrate, wherein a bottom surface of a recessed portion provided between respective ones of the plurality of ridge-shaped nitride semiconductor layers is the m-plane of the sapphire substrate, the growing plane of the plurality of ridge-shaped nitride semiconductor layers is an m-plane, and an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor layers and a c-axis of the sapphire substrate is not less than 0° and not more than 35°.

Claims (52)

1. A multilayer structure, comprising:

a structure for growth of a nitride semiconductor layer; and

a nitride semiconductor layer, wherein

the structure for growth of the nitride semiconductor layer comprises:

a sapphire substrate having a growing plane which is an m-plane; and

a plurality of ridge-shaped nitride semiconductor regions formed on the growing plane of the sapphire substrate;

a bottom surface of a recessed portion provided between respective ones of the plurality of ridge-shaped nitride semiconductor regions is the m-plane of the sapphire substrate;

a growing plane of the plurality of ridge-shaped nitride semiconductor regions is an m-plane;

an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor regions and a c-axis of the sapphire substrate is not less than 5° and not more than 35°;

a back surface of the nitride semiconductor layer is in contact with the plurality of the ridge-shaped nitride semiconductor regions; and

a front surface of the nitride semiconductor layer has a surface rms roughness of not more than 100 nanometers.

2. The multilayer structure according to claim 1 , wherein

an angle inside the plurality of ridge-shaped nitride semiconductor regions between a lateral surface which is parallel to the extending direction of the plurality of ridge-shaped nitride semiconductor regions and the m-plane is greater than 0° and smaller than 150°.

3. The multilayer structure according to claim 1 , wherein

a depth of the bottom surface relative to an interface between the sapphire substrate and the ridge-shaped nitride semiconductor regions is more than 0 nm and not more than 150 nm.

4. The multilayer structure according to claim 1 , wherein

an angle between the extending direction of the plurality of ridge-shaped nitride semiconductor regions and the c-axis of the sapphire substrate is not less than 0° and not more than 10°.

5. The multilayer structure according to claim 1 , wherein

a value of S width/(L width+S width) is not less than 0.6 and less than 1,

where L width represents a width of the plurality of ridge-shaped nitride semiconductor regions at a base, and

S width represents a width of the recessed portions at a bottom surface.

6. The multilayer structure according to claim 1 , wherein

an upper surface of the plurality of ridge-shaped nitride semiconductor regions is not provided with a mask.

7. The multilayer structure according to claim 1 , further comprising a buffer layer provided between the growing plane of the sapphire substrate and the ridge-shaped nitride semiconductor regions, the buffer layer being formed of Al x Ga y In z N, where 0≦x, y, z≦1, x+y+z=1.

8. The multilayer structure according to claim 1 , wherein

the back surface of the nitride semiconductor layer is in contact with an upper surface of the plurality of ridge-shaped nitride semiconductor regions.

9. A nitride-based semiconductor light-emitting device comprising the multilayer structure as set forth in claim 1 .

10. The multilayer structure according to claim 5 , wherein

the L width is not less than 0.1 μm and not more than 10 μm,

the S width is not less than 0.15 μm and not more than 30 μm, and

the value of S width/(L width+S width) is not less than 0.6 and not more than 0.996.

11. The multilayer structure according to claim 5 , wherein

the L width is not less than 0.1 μm and not more than 10 μm,

the S width is not less than 30 μm and not more than 300 μm, and

the value of S width/(L width+S width) is not less than 0.75 and less than 1.

12. The multilayer structure according to claim 5 , wherein

the L width is not less than 1 μm and not more than 5 μm,

the S width is not less than 30 μm and not more than 300 μm, and

the value of S width/(L width+S width) is not less than 0.857 and less than 1.

13. The multilayer structure according to claim 7 , wherein

the buffer layer is not present on a bottom surface or lateral surface of the recessed portions.

14. The multilayer structure according to claim 7 , wherein the buffer layer is formed of AIN.

15. A light source, comprising:

the nitride-based semiconductor light-emitting device as set forth in claim 9 ; and

a wavelength converter including a phosphoric material which is capable of converting a wavelength of light emitted from the nitride-based semiconductor light-emitting device.

16. A method for fabricating a multilayer structure, comprising the steps of:

(a) providing a sapphire substrate having a growing plane which is an m-plane;

(b) growing a nitride semiconductor film on the growing plane of the sapphire substrate;

(c) forming a plurality of recessed portions so as to penetrate through the nitride semiconductor film, thereby forming a plurality of ridge-shaped nitride semiconductor regions; and

(d) growing a nitride semiconductor layer such that the growth starts from the plurality of ridge-shaped nitride semiconductor regions,

wherein in the step (c), the plurality of recessed portions are formed such that a bottom surface of the plurality of recessed portions is the m-plane of the sapphire substrate, the growing plane of the plurality of ridge-shaped nitride semiconductor regions is an m-plane, and an absolute value of an angle between an extending direction of the plurality of ridge-shaped nitride semiconductor regions and a c-axis of the sapphire substrate is not less than 5° and not more than 35°; and

in the step (d), a front surface of the nitride semiconductor layer has a surface rms roughness of not more than 100 nanometers.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2014
From: CHOE, SONGBAEK; YOKOGAWA, TOSHIYA; INOUE, AKIRA; YAMADA, ATSUSHI
To: PANASONIC CORPORATION
Reel/Frame 032261/0121 →