Clock generator for use in a time-interleaved ADC and methods for use therewith
View Patent ↗A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.
1. A clock generator comprising:
a first clock generator configured to receive an input clock, to generate a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor and to generate a time-leading version of the first clock signal;
a plurality of second clock generators configured to receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit, wherein the plurality of second level clock generators include:
an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal; and
a feedback controller, coupled to the adjustable delay, configured to generate the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.
2. The clock generator of claim 1 wherein the feedback controller controls a falling edge of the corresponding one of the plurality of second clock signals to occur before a falling edge of the first clock signal.
3. The clock generator of claim 1 wherein the feedback controller controls a rising edge of the corresponding one of the plurality of second clock signals to occur after a rising edge of the first clock signal.
4. The clock generator of claim 1 wherein the feedback controller includes a first flip-flop triggered by a rising edge of the corresponding one of the plurality of second clock signals that captures a first value of the time-leading version of the first clock signal.
5. The clock generator of claim 4 wherein the feedback controller further includes a second flip-flop triggered by a falling edge of the corresponding one of the plurality of second clock signals that captures a second value of the time-leading version of the first clock signal.
6. The clock generator of claim 5 wherein the feedback controller further includes logic that generates the delay control signal to indicate one of: a command to increase the delay amount, a command to maintain the delay amount and a command to decrease the delay amount.
7. The clock generator of claim 1 wherein the plurality of second clock generators generate the corresponding plurality of second clock control signals based on an inversion of the input clock.
8. The clock generator of claim 1 wherein the first clock generator includes a delay line having a plurality of delay elements and a tap at least one delay element prior to the output and wherein the first clock signal is generated at the output of the delay line and the time-leading version of the first clock signal is generated at the tap.
9. A method comprising:
generating, based on an input clock, a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor and a time-leading version of the first clock signal;
generating, based on the input clock, a plurality of second clock signals for use in a second level of the multi-level track and hold circuit by:
delaying the plurality of second clock signals by corresponding ones of a plurality of delay amounts that are determined based on corresponding ones of a plurality of delay control signals; and
generating the plurality of delay control signals based on the time-leading version of the first clock signal and further based on corresponding ones of the plurality of second clock signals.
10. The method of claim 9 wherein the plurality of delay control signals are generated to control a falling edge of the corresponding one of the plurality of second clock signals to occur before a falling edge of the first clock signal.
11. The method of claim 9 wherein the plurality of delay control signals are generated to control a rising edge of the corresponding one of the plurality of second clock signals to occur after a rising edge of the first clock signal.
12. The method of claim 9 wherein the plurality of delay control signals are generated to indicate one of: a command to increase the delay amount, a command to maintain the delay amount and a command to decrease the delay amount.
13. The method of claim 9 wherein the plurality of second clock control signals is generated based on an inversion of the input clock.
14. A clock generator comprising:
a first clock generator configured to receive an input clock, to generate a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, wherein the first clock generator includes a delay line having a plurality of delay elements and a tap at least one delay element prior to the output and wherein the first clock signal is generated at the output of the delay line and a time-leading version of the first clock signal is generated at the tap;
a plurality of second clock generators configured to receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit, wherein the plurality of second level clock generators include:
an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal; and
a feedback controller, coupled to the adjustable delay, configured to generate the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.
15. The clock generator of claim 14 wherein the feedback controller controls a falling edge of the corresponding one of the plurality of second clock signals to occur before a falling edge of the first clock signal.
16. The clock generator of claim 14 wherein the feedback controller controls a rising edge of the corresponding one of the plurality of second clock signals to occur after a rising edge of the first clock signal.
17. The clock generator of claim 14 wherein the feedback controller includes a first flip-flop triggered by a rising edge of the corresponding one of the plurality of second clock signals that captures a first value of the time-leading version of the first clock signal.
18. The clock generator of claim 17 wherein the feedback controller further includes a second flip-flop triggered by a falling edge of the corresponding one of the plurality of second clock signals that captures a second value of the time-leading version of the first clock signal.
19. The clock generator of claim 18 wherein the feedback controller further includes logic that generates the delay control signal to indicate one of: a command to increase the delay amount, a command to maintain the delay amount and a command to decrease the delay amount.
20. The clock generator of claim 14 wherein the plurality of second clock generators generate the corresponding plurality of second clock control signals based on an inversion of the input clock.