IP Library Granted Patent US 9,087,569
Granted Patent B2
US 9,087,569 · App. 14/089,858 · Granted Jul 21, 2015

Non-volatile memory validity

Inventor: Mark Charles Davis (Durham, NC)
Assignee: Lenovo (Singapore) Pte. Ltd.
G11C7/22G11C11/406G11C13/0033G11C13/0035
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Quick Facts
Patent No.
US 9,087,569
App. No.
14/089,858
Granted
Jul 21, 2015
Kind
B2
Abstract

An embodiment provides a method, including: determining current validity timing of a non-volatile memory device having changing validity timing via: writing information to a non-volatile memory device; waiting a time after the writing; and reading the information written to the non-volatile memory device following the time. Other aspects are described and claimed.

Claims (48)

1. A method, comprising:

determining current validity timing of a non-volatile memory device having changing validity timing via:

writing test information to a non-volatile memory device;

waiting a predetermined time after the writing; and

reading the test information written to the non-volatile memory device following the predetermined time.

2. The method of claim 1 , wherein the test information written to the non-volatile memory device includes timing information.

3. The method of claim 2 , wherein the determining comprises comparing the timing information to a current time.

4. The method of claim 3 , further comprising:

determining that an elapsed time since a last refresh of the non-volatile memory device exceeds a predetermined time using the timing information and the current time; and

performing a refresh of the non-volatile memory device.

5. The method of claim 2 , wherein the determining is performed by a memory controller.

6. The method of claim 1 , further comprising:

determining the current validity time has been exceeded; and

providing an indication that the current validity timing has been exceeded.

7. The method of claim 1 , wherein the test information written to the non-volatile memory device includes a test bit.

8. The method of claim 7 , wherein the determining comprises comparing the test bit to an expected value.

9. The method of claim 8 , further comprising:

determining that the test bit does not match the expected value; and

updating a life expectancy estimate for the non-volatile memory device.

10. The method of claim 1 , wherein the non-volatile memory is a memory device selected from the group of memory devices consisting of non-volatile random access memory (NVRAM), magneto-resistive random access memory (MRAM), spin transfer torque random access memory (STT-RAM), and resistive random access memory (ReRAM).

11. An information handling device, comprising:

a non-volatile memory device;

a processor; and

a memory device storing instructions executable by the processor to:

determine current validity timing of the non-volatile memory device, the non-volatile memory device having changing validity timing via:

write test information to the non-volatile memory device;

wait a predetermined time after the writing; and

read the test information written to the non-volatile memory device following the predetermined time.

12. The information handling device of claim 11 , wherein the predetermined information written to the non-volatile memory device includes timing information.

13. The information handling device of claim 12 , wherein to determine comprises comparing the timing information to a current time.

14. The information handling device of claim 13 , wherein the instructions are further executable by the processor to:

determine that an elapsed time since a last refresh of the non-volatile memory device exceeds a predetermined time using the timing information and the current time; and

perform a refresh of the non-volatile memory device.

15. The information handling device of claim 12 , wherein the current validity timing is determined by a memory controller.

16. The information handling device of claim 11 , wherein the instructions are further executable by the processor to:

determine the current validity time has been exceeded; and

provide an indication that the current validity timing has been exceeded.

17. The information handling device of claim 11 , wherein the test information written to the non-volatile memory device includes a test bit.

18. The information handling device of claim 17 , wherein to determine comprises comparing the test bit to an expected value.

19. The information handling device of claim 18 , wherein the instructions are further executable by the processor to:

determine that the test bit does not match the expected value; and

update a life expectancy estimate for the non-volatile memory device.

20. A program product, comprising:

a storage medium comprising computer readable program code, the computer readable program code comprising:

computer readable program code configured to determine current validity timing of a non-volatile memory device having changing validity timing via:

writing test information to a non-volatile memory device;

waiting a predetermined time after the writing; and

reading the test information written to the non-volatile memory device following the predetermined time.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2025
From: LENOVO PC INTERNATIONAL LIMITED
To: LENOVO SWITZERLAND INTERNATIONAL GMBH
Reel/Frame 069870/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2019
From: LENOVO (SINGAPORE) PTE. LTD.
To: LENOVO PC INTERNATIONAL
Reel/Frame 049687/0855 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 26, 2013
From: DAVIS, MARK CHARLES
To: LENOVO (SINGAPORE) PTE. LTD.
Reel/Frame 031675/0662 →
Continuity (1)
Related Publication 20150146493A1 · May 28, 2015