Distortion estimation and cancellation in memory devices
A method for operating a memory ( 28 ) includes storing data in a group of analog memory cells ( 32 ) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.
1. An apparatus, comprising:
an interface configured to communicate with a memory, wherein the memory includes a plurality of memory cells; and
a processor coupled to the interface, wherein the processor is configured to:
identify one or more memory cells of a subset of the plurality of memory cells, wherein each memory cell of the one or more memory cells was programmed subsequent to a programming of another memory cell of the subset of the plurality of memory cells;
read one or more values from a respective memory cell of the one or more memory cells of the subset of the plurality of memory cells of the memory, wherein the read values correspond to data stored in the one or more memory cells;
estimate distortion levels in the read one or more values by estimating values for one or more cross-coupling coefficients by sequentially reducing a distance metric between the read one or more values and corresponding hard decisions;
read another value from the another memory cell of the subset of the plurality of memory cells, wherein the read another value corresponds to data stored in the another memory cell;
predict a distortion level in the read another value dependent upon the estimated distortion levels in the read one or more values;
adjust the read value from the another memory cell dependent upon the predicted distortion level; and
reconstruct the data stored in the another memory cell dependent upon the adjusted read value from the another memory cell.
2. The apparatus of claim 1 , wherein the data stored in the another memory cell is encoded with an Error Correction Code (ECC).
3. The apparatus of claim 1 , wherein to predict the distortion level in the read another value, the processor is further configured to compare a value of a parameter relating to the another memory cell measured at a time when the another memory cell was programmed to a value of the parameter relating to the memory cell measured at a time when the another memory cell was read.
4. The apparatus of claim 1 , wherein to predict the distortion level in the read another value, the processor is further configured to:
track one or more parameters common to the subset of the plurality of memory cells; and
store the tracked one or more parameters in a data structure.
5. The apparatus of claim 1 , wherein each memory cell of the subset of the plurality of memory cells is coupled to a common bit line.
6. The apparatus of claim 1 , wherein each memory cell of the plurality of memory cells comprises a non-volatile memory cell.
7. A method for operating a memory, the method comprising:
identifying one or more memory cells of a subset of a plurality of memory cells, wherein each memory cell of the one or more memory cells was programmed subsequent to a programming of another memory cell of the subset of the plurality of memory cells
reading one or more values from a respective memory cell of the one or more memory cells of the subset of the plurality of memory cells of the memory, wherein the read values correspond to data stored in the one or more memory cells;
estimating distortion levels in the read one or more values, wherein estimating the distorion levels in the read one or more values includes estimating values for one or more cross-coupling coefficients by sequentially reducing a distance metric between the read one or more values and corresponding hard decisions;
reading another value from the another memory cell of the subset of the plurality of memory cells, wherein the read another value corresponds to data stored in the another memory cell;
predicting a distortion level in the read another value dependent upon the estimated distortion levels in the read one or more values;
adjusting the read value from the another memory cell dependent upon the predicted distortion level; and
reconstructing the data stored in the another memory cell dependent upon the adjusted read value from the another memory cell.
8. The method of claim 7 , wherein the data stored in the another memory cell is encoded with an Error Correction Code (ECC).
9. The method of claim 7 , wherein predicting the distortion level in the read another value comprises comparing a value of a parameter relating to the another memory cell measured at a time when the another memory cell was programmed to a value of the parameter relating to the memory cell measured at a time when the another memory cell was read.
10. The method of claim 7 , wherein predicting the distortion level in the read another value comprises:
tracking one or more parameters common to the subset of the plurality of memory cells; and
storing the tracked one or more parameters in a data structure.
11. The method of claim 7 , wherein each memory cell of the subset of the plurality of memory cells is coupled to a common bit line.
12. The method of claim 7 , wherein each memory cell of the subset of the plurality of memory cells is coupled to common circuitry.
13. The method of claim 7 , wherein each memory cell of the plurality of memory cells comprises a non-volatile memory cell.
14. A system, comprising:
a memory including a plurality of memory cells; and
a controller coupled to the memory, wherein the controller is configured to:
identify one or more memory cells of a subset of the plurality of memory cells,
wherein each memory cell of the one or more memory cells was programmed subsequent to a programming of another memory cell of the subset of the plurality of memory cells;
read one or more values from a respective memory cell of the one or more memory cells of the subset of the plurality of memory cells of the memory, wherein the read values correspond to data stored in the one or more memory cells;
estimate distortion levels in the read one or more values by estimating values for one or more cross-coupling coefficients by sequentially reducing a distance metric between the read one or more values and corresponding hard decisions;
read another value from the another memory cell of the subset of the plurality of memory cells, wherein the read another value corresponds to data stored in the another memory cell;
predict a distortion level in the read another value dependent upon the estimated distortion levels in the read one or more values;
adjust the read value from the another memory cell dependent upon the predicted distortion level; and
reconstruct the data stored in the another memory cell dependent upon the adjusted read value from the another memory cell.
15. The system of claim 14 , wherein the data stored in the another memory cell is encoded with an Error Correction Code (ECC).
16. The system of claim 14 , wherein to predict the distortion level in the read another value, the controller is further configured to compare a value of a parameter relating to the another memory cell measured at a time when the another memory cell was programmed to a value of the parameter relating to the memory cell measured at a time when the another memory cell was read.
17. The system of claim 14 , wherein to predict the distortion level in the read another value, the controller is further configured to:
track one or more parameters common to the subset of the plurality of memory cells; and
store the tracked one or more parameters in a data structure.
18. The system of claim 14 , wherein each memory cell of the subset of the plurality of memory cells is coupled to a common bit line.
19. The system of claim 14 , wherein each memory cell of the subset of the plurality of memory cells is coupled to a common word line.
20. The system of claim 14 , wherein each memory cell of the plurality of memory cells comprises a non-volatile memory cell.