Efficient LDPC codes
A method includes accepting a definition of a mother Error Correction Code (ECC) that is represented by a set of parity check equations and includes first code words, and a definition of a punctured ECC that includes second code words and is derived from the mother ECC by removal of one or more of the parity check equations and removal of one or more punctured check symbols selected from among check symbols of the first code words. A mother decoder, which is designed to decode the mother ECC by exchanging messages between symbol nodes and check nodes in accordance with a predefined interconnection scheme that represents the mother ECC, is provided. An input code word of the punctured ECC is decoded using the mother decoder by initializing one or more of the symbol nodes and controlling one or more of the messages, and while retaining the interconnection scheme.
1. An apparatus, comprising:
a check node memory configured to store check nodes;
a symbol node memory configured to store symbol nodes; and
a control unit coupled to the check node memory and the symbol node memory, wherein the control unit includes circuitry configured to:
receive a first Error Correction Code (ECC), wherein the first ECC is defined by a first set of parity equations;
receive a plurality of input code words, wherein each input code word of the plurality of input code words is encoded with a second ECC, wherein the second ECC is defined by a second set of parity equations, wherein the second set of parity equations is a proper subset of the first set of parity equations;
receive an indication of parity equations included in the first set of parity equations but excluded from the second set of parity equations;
and
decode, iteratively, each input code word of the received plurality of input code words dependent upon messages transferred between the symbol node memory and the check node memory, wherein the messages transferred between the symbol node memory and the check node memory are controlled such that messages originating from check nodes that correspond to parity check equations excluded from the second set of parity equations are prevented from affecting the symbol nodes by assigning to symbol nodes respective artificial confidence metrics that indicate a zero value with a maximal likelihood based upon the received indication of the parity equations included in the first set of parity equations but excluded from the second set of parity equations.
2. The apparatus of claim 1 , wherein the first ECC code includes a first set of possible data symbols and a first set of possible check symbols.
3. The apparatus of claim 2 , wherein the control unit is further configured to receive a second set of possible data symbols, wherein the second set of possible data symbols is a proper subset of the first set of possible data symbols.
4. The apparatus of claim 2 , wherein the control unit is further configured to receive a second set of possible check symbols, wherein the second set of possible check symbols is a proper subset of the first set of possible check symbols.
5. The apparatus of claim 1 , wherein each input code word of the plurality of input code words includes at least one data symbol and at least one check symbol, and wherein to decode, iteratively, each input code word of the plurality of input code words the control unit is further configured to calculate, for each symbol included in each input code word of the plurality of input code words, a Log Likelihood Ratio (LLR).
6. A method, comprising:
initializing a decoder with a first Error Correction Code (ECC), wherein the first ECC is defined by a first set of parity equations;
receiving a plurality of input code words, wherein each input code word of the plurality of input code words is encoded with a second ECC, wherein the second ECC is defined by a second set of parity equations, wherein the second set of parity equations is a proper subset of the first set of parity equations;
receiving an indication of which parity equations are included in the first set of parity equations but excluded from the second set of parity equations;
and
decoding, iteratively, each input code word of the received plurality of input code words based upon messages transferred between the symbol node memory and the check node memory, wherein the messages transferred between the symbol node memory and the check node memory are controlled such that messages originating from check nodes that correspond to parity check equations excluded from the second set of parity equations are prevented from affecting the symbol nodes by assigning to symbol nodes respective artificial confidence metrics that indicate a zero value with a maximal likelihood based upon the received indication of the parity equations included in the first set of parity equations but excluded from the second set of parity equations.
7. The method of claim 6 , wherein the first ECC code includes a first set of possible data symbols and a first set of possible check symbols.
8. The method of claim 7 , wherein initializing the decoder with the first ECC comprises receiving a second set of possible data symbols, wherein the second set of possible data symbols is a proper subset of the first set of possible data symbols.
9. The method of claim 7 , wherein initializing the decoder with the first ECC comprises receiving a second set of possible check symbols, wherein the second set of possible check symbols is a proper subset of the first set of possible check symbols.
10. The method of claim 6 , wherein each input code word of the plurality of input code words includes at least one data symbol and at least one check symbol.
11. The method of claim 10 , wherein decoding, iteratively, each input code word of the plurality of input code words comprises calculating, for each symbol included in each input code word of the plurality of input code words, a Log Likelihood Ratio (LLR).
12. A system, comprising:
a memory; and
a memory controller coupled to the memory, wherein the memory controller is configured to:
receive a first Error Correction Code (ECC), wherein the first ECC is defined by a first set of parity equations;
receive a plurality of input code words wherein each input code word of the plurality of input code words is encoded with a second ECC, wherein the second ECC is defined by a second set of parity equations, wherein the second set of parity equations is a proper subset of the first set of parity equations;
receive an indication of parity equations included in the first set of parity equations but excluded from the second set of parity equations;
wherein the memory controller includes circuitry configured to decode, iteratively, each input code word of the received plurality of input code words dependent upon messages transferred between a symbol node memory configured to store symbol nodes and a check node memory configured to store check nodes, wherein the circuitry is configured to control the messages transferred between the symbol node memory and the check node memory such that messages originating from check nodes that correspond to parity check equations excluded from the second set of parity equations are prevented from affecting the symbol nodes by assigning to symbol nodes respective artificial confidence metrics that indicate a zero value with a maximal likelihood based upon the received 5 indication of the parity equations included in the first set of parity equations but excluded from the second set of parity equations; and
send each decoded input code word to the memory.
13. The system of claim 12 , wherein the first ECC code includes a first set of possible data symbols and a first set of possible check symbols.
14. The system of claim 13 , wherein the memory controller is further configured to receive a second set of possible data symbols, wherein the second set of possible data symbols is a proper subset of the first set of possible data symbols.
15. The system of claim 13 , wherein the memory controller is further configured to receive a second set of possible check symbols, wherein the second set of possible check symbols is a proper subset of the first set of possible check symbols.
16. The system of claim 12 , wherein each input code word of the plurality of input code words includes at least one data symbol and at least one check symbol, and wherein to decode, iteratively, each code input word of the plurality of input code words the memory controller is further configured to calculate, for each symbol included in each input code word of the plurality of input code words, a Log Likelihood Ratio (LLR).
17. The system of claim 12 , wherein the memory comprises a non-volatile memory.