Duty rate detecter and semiconductor device using the same

1. A duty rate detection circuit comprising:

a duty rate detection block suitable for outputting a duty rate detection signal by detecting a duty rate of a clock signal having a first logic duration and a second logic duration; and

an output control block suitable for comparing the number of the first logic duration and the number of the second logic duration for a detection period and controlling an output moment of the duty rate detection signal,

wherein the duty rate detection block includes a duty rate discharge unit for performing a discharge operation during each of the first logic duration and the second logic duration and is designed as a current mirror type.

2. The duty rate detection circuit of claim 1 , wherein the duty rate detection block further includes:

an output unit for outputting the duty rate detection signal based on an output signal of the duty rate discharge unit output at an end of the detection period.

3. The duty rate detection circuit of claim 2 , wherein the duty rate discharge unit includes:

a first discharger for discharging a first output terminal during the first logic duration;

a second discharger for discharging a second output terminal during the second logic duration; and

a charger for charging the first output terminal and the second output terminal in response to a strobe signal.

4. The duty rate detection circuit of claim 3 , wherein the duty rate detection block further includes a strobe signal generation unit for generating the strobe signal in synchronization with the first logic duration.

5. The duty rate detection circuit of claim 4 , wherein the output control block includes:

a level detection unit for detecting voltage levels of the first output terminal and the second output terminal discharged to a predetermined target voltage level; and

a synchronization unit for synchronizing an output signal of the level detection unit to the first logic duration and generating a time control signal defining the detection period.

6. A semiconductor device comprising:

a duty rate discharge unit suitable for performing a discharge operation in a first output terminal and a second output terminal during a first logic duration and a second logic duration of a clock signal, respectively;

a level detection unit suitable for detecting voltage levels of the first output terminal and the second output terminal discharged to a predetermined target voltage level;

an output unit suitable for detecting a duty rate of the clock signal at a moment when the number of the first logic duration and the number of the second logic duration representing the discharge operation time become the same after an output signal of the level detection unit is enabled; and

a locking information generation unit suitable for generating duty locking information by comparing the output signal of the level detection unit with an output signal of the output unit.

7. The semiconductor device of claim 6 , wherein the duty locking information is enabled when the output signal of the level detection unit and the output signal of the output unit represent different logic durations of first logic duration and the second logic duration of the clock signal.

8. The semiconductor device of claim 6 , wherein the duty rate discharge unit includes:

a first discharger for discharging the first output terminal during the first logic duration;

a second discharger for discharging the second output terminal during the second logic duration; and

a charger for charging the first output terminal and the second output terminal in response to a strobe signal.

9. The semiconductor device of claim 8 , further comprising a strobe signal generation unit suitable for generating the strobe signal in synchronization with the first logic duration.

10. The semiconductor device of claim 8 , further comprising a synchronization unit suitable for synchronizing an output signal of the level detection unit to the first logic duration and generating a time control signal defining the moment when the number of the first logic duration and the number of the second logic duration representing the discharge operation time become the same after an output signal of the level detection unit is enabled.

11. The semiconductor device of claim 6 , wherein the duty rate discharge unit is designed as a current mirror type.

12. A duty rate detection circuit comprising:

a duty rate discharge unit suitable for respectively discharging a first terminal therein and a second terminal therein having corresponding predetermined voltage levels for corresponding duration between a first logic duration and a second logic duration of a clock signal;

an output control unit suitable for generating a discharge detection signal synchronized with the first logic duration when one of the first terminal and the second terminal is discharged to a reference voltage level; and

an output unit suitable for detecting in response to the discharge detection signal synchronized with the first logic duration a duty rate of the clock signal based on the clock signal having toggled until the discharge detection signal is synchronized with the first logic duration,

wherein, the duty rate discharge unit begin discharging in synchronized with the first logic duration.

13. The duty rate detection circuit of claim 12 , wherein the duty rate discharge unit includes:

a charger for charging the first terminal and the second terminal to the corresponding predetermined voltage levels;

a first discharger for discharging the first terminal during the first logic duration; and

a second discharger for discharging the second terminal during the second logic duration.

14. The duty rate detection circuit of claim 12 , wherein the output control block includes:

a level detection unit for generating the discharge detection signal when one of the first terminal and the second terminal is discharged to a reference voltage level; and

a synchronization unit for synchronizing the discharge detection signal to the first logic duration.