Secure processor and a program for a secure processor
View Patent ↗The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.
1. A processor comprising:
an execution unit configured to output a first virtual address;
a mode register configured to indicate whether the processor is in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited; and
a memory access control unit configured to output a first physical address corresponding to the first virtual address by referring to either a first translation look aside buffer for the first mode or a second translation look aside buffer for the second mode in accordance with a value of the mode register,
wherein, by executing a first instruction code stored in the secure address space in the first mode, a second instruction code is checked in the first mode before the second instruction code is executed in the second mode, and
wherein, in the second mode, the memory access control unit prohibits an access to a physical address within the secure address space in accordance with the second translation look aside buffer.
2. The processor according to claim 1 ,
wherein the first instruction code is stored in a non-rewritable memory.
3. The processor according to claim 1 ,
wherein a mode switching between the first mode and the second mode is triggered by an interruption.
4. The processor according to claim 3 ,
wherein the mode register is set in response to the interruption.
5. The processor according to claim 1 ,
wherein each of the first translation look aside buffer and the second translation look aside buffer includes a plurality of page table entries and each of the page table entries includes a physical address, a virtual address corresponding to the physical address, and an identifier that each indicate the first mode or the second mode.
6. The processor according to claim 1 ,
wherein the second instruction code is executed in the second mode after the second instruction code is checked.
7. The processor according to claim 1 ,
wherein the first mode is a secure mode and the second mode is a normal mode.
8. A processor connprising:
an execution unit configured to output a first virtual address;
a mode register configured to indicate whether the processor is in a first mode in which an access to a secure address space is permitted or in a second mode in which an access to the secure address space is prohibited; and
a memory access control unit configured to output a first physical address corresponding to the first virtual address by referring to either a first translation look aside buffer for the first mode or a second translation look aside buffer for the second mode in accordance with a value of the mode register,
wherein, by executing a first instruction code stored in the secure address space in the first mode, an second instruction code is checked in the first mode, and the second instruction code is executed in the second mode after the second instruction code is checked, and
wherein, in the second mode, the memory access control unit prohibits an access to a physical address within the secure address space in accordance with the second translation look aside buffer.
9. The processor according to claim 8 ,
wherein a mode switching between the first mode and the second mode is triggered by an interruption.
10. The processor according to claim 9 ,
wherein the mode register is set in response to the interruption.
11. The processor according to claim 8 ,
wherein the first mode is a secure mode and the second mode is a normal mode.