Optimizing system throughput by automatically altering thread co-execution based on operating system directives
View Patent ↗A technique for optimizing program instruction execution throughput in a central processing unit core (CPU). The CPU implements a simultaneous multithreading (SMT) operational mode wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing one or more hardware resources used by the CPU, such as cache memory, translation lookaside buffers, functional execution units, etc. As part of the SMT mode, the CPU implements an autothread (AT) operational mode. During the AT operational mode, a determination is made whether there is a resource conflict between the hardware threads that undermines instruction execution throughput. If a resource conflict is detected, the CPU adjusts the relative instruction execution rates of the hardware threads based on relative priorities of the software threads.
1. A method for optimizing program instruction execution throughput in a processor apparatus having at least one central processing unit core (CPU), comprising:
implementing a simultaneous multithreaded (SMT) operational mode in said CPU wherein program instructions associated with at least two software threads are executed in parallel as hardware threads while sharing a cache memory resource within said CPU;
implementing an autothread (AT) operational mode in said CPU;
determining as part of said AT operational mode (1) whether there is a resource conflict between said hardware threads, and (2) whether said resource conflict undermines instruction execution throughput; and
if said determining detects a resource conflict that undermines instruction execution throughput, adjusting relative instruction execution rates of said hardware threads in said CPU based on relative priorities of said software threads specified to said processor apparatus by a software scheduling entity.
2. The method of claim 1 , wherein said resource conflict determining comprises determining whether one or more of a cache eviction rate, a translation lookaside buffer eviction rate, or contention for functional execution units associated with said CPU exceeds a threshold, and whether an instruction retiral rate of said hardware threads is below an instruction retiral rate threshold.
3. The method of claim 1 , wherein said resource conflict determining is performed periodically at a predetermined interval.
4. The method of claim 1 , wherein said instruction execution rate adjusting comprises throttling an instruction fetch rate of one or more lower priority threads.
5. The method of claim 1 , further including readjusting said relative instruction execution rates of said hardware threads in said CPU if said instruction execution rate adjusting does not improve an instruction retiral rate of one or more threads.
6. The method of claim 1 , further including exiting said AT mode when said CPU is not executing in application thread context.
7. The method of claim 1 , further including logging an amount of time said at least two software threads are allowed to execute for use in subsequent software scheduling of said software threads, said software scheduling including increasing a priority of a first software thread whose instruction execution throughput was decreased during AT mode processing and decreasing a priority of a second software thread whose instruction execution throughput was increased during AT mode processing.