Method for setting transistor operating point and circuit therefor, method for changing signal component value and active-matrix liquid crystal display device
A data signal voltage on a signal line is held in a voltage holding capacitor through an n-type MOS transistor switched on by a gate scan voltage, and supplied to an analog amplifier circuit. The analog amplifier circuit is formed of an MOS transistor having a double gate structure, and the operating point thereof is set at an operating range in which dependence of Ids on Vds is substantially nullified. Even when Vds is varied due to a response of liquid crystal, Ids is substantially fixed. Accordingly, the pixel voltage which is substantially proportional to the data signal voltage can be applied to the liquid crystal.
1. A method for setting the operating point of a unipolar first transistor, wherein the unipolar first transistor having a multi-gate structure is equivalently achieved by commonly connecting respective gates of plural unipolar second transistors each having a single gate structure and connecting the plural unipolar second transistors to one another in series, an operating point of each single unipolar second transistor having the single gate structure is set at an operating point that the dependence of source-drain current on source-drain voltage is within a permissible range.
2. The method according to claim 1 , wherein said unipolar first transistor having the multi-gate structure is an insulated gate type transistor having a multi-gate structure or a junction type transistor having a multi-gate structure.
3. The method according to claim 1 , wherein the operating point is set at any one of an optimum operating point within the permissible range and an operating point other than the optimum operating point within the permissible range.
4. The method according to claim 1 , wherein said unipolar first transistor having the multi-gate structure alters the signal component value of a signal, the signal being any one of an amplified signal, a modulated signal and a demodulated signal.
5. The method according to claim 1 , wherein said unipolar first transistor is connected to a load element and the load element is a unipolar third transistor.
6. The method according to claim 5 , wherein a gate of the unipolar third transistor is configured for receiving a first voltage, a drain of the third transistor is connected to drain of the unipolar first transistor, and a source of the unipolar third transistor is configured for receiving a second voltage.
7. The method according to claim 5 , wherein a gate of the unipolar third transistor is configured for receiving a third voltage, a drain of the third transistor is connected to drain of the unipolar first transistor, and a source of the unipolar third transistor is configured for receiving a fourth voltage.
8. A method for changing a signal component value of an input signal by using a unipolar first transistor, wherein a unipolar first transistor having a multi-gate structure is equivalently achieved by commonly connecting respective gates of plural unipolar second transistors each having a single gate structure and connecting the plural unipolar second transistors to one another in series, an operating point of each single unipolar first transistor having the single gate structure is set at an operating point that the dependence of source-drain current on source-drain voltage is within a permissible range, and said unipolar first transistor having the multi-gate structure is operated at the operating point and set to change the signal component value of the input signal.
9. The method according to claim 8 , wherein the number of said unipolar first transistor having the multi-gate structure for which the operating point is set is a singular number or a plural number.
10. The method according to claim 8 , wherein said unipolar first transistor having the multi-gate structure is selected from a group consisting of an insulated gate type transistor having a multi-gate structure and a junction type transistor having a multi-gate structure.
11. The method according to claim 8 , wherein the operating point is set at any one of an optimum operating point within the permissible range and an operating point other than the optimum operating point within the permissible range.
12. The method according to claim 8 , wherein the signal is any one of an amplified signal, a modulated signal and a demodulated signal.
13. The method according to claim 8 , wherein the signal component of the signal is any one of the amplitude, phase and frequency of the signal.
14. The method according to claim 8 , wherein said unipolar first transistor is connected to a load element, and the load element is a unipolar third transistor.
15. The method according to claim 8 , wherein a gate of the unipolar third transistor is configured for receiving a first voltage, a drain of the third transistor is connected to drain of the unipolar first transistor, and a source of the unipolar third transistor is configured for receiving a second voltage.
16. The method according to claim 8 , wherein a gate of the unipolar third transistor is configured for receiving a third voltage, a drain of the third transistor is connected to drain of the unipolar first transistor, and a source of the unipolar third transistor is configured for receiving a fourth voltage.
17. A circuit for setting the operating point of a unipolar transistor, wherein a unipolar transistor having a multi-gate structure is equivalently achieved by commonly connecting respective gates of plural unipolar transistors each having a single gate structure and connecting the plural unipolar transistors to one another in series, an operating point of each single unipolar transistor having the single gate structure is set at an operating point that the dependence of source-drain current on source-drain voltage is within a permissible range.
18. The circuit according to claim 17 , wherein the unipolar transistor having the multi-gate structure is an insulated gate type transistor having a multi-gate structure or a junction type transistor having a multi-gate structure.
19. The circuit according to claim 17 , wherein the operating point is set at any one of an optimum operating point within the permissible range and an operating point other than the optimum operating point within the permissible range.