Apparatus for faster division
View Patent ↗A system and method for reducing central processing unit transistor count when dividing multiple floating point numbers is disclosed. An example system may receive a plurality of floating point numbers to be inverted as denominator values. The denominator values may be grouped into pairs and multiplied. Products of pairs may be multiplied to produce combinations of products of denominator values until all denominator values have been multiplied together. The product of all denominator values may be inverted using a single division. The combinations of products of denominator values from the multiplications achieved before the division may be multiplied with the inverted product from the division to compute inversions of all denominator values. In some embodiments, an example system may receive a plurality of floating point numbers as numerator values that each correspond to a denominator value. Numerator values may be multiplied with corresponding inversion denominator values to produce division results.
1. An apparatus for reducing central processing unit usage when inverting numbers, the apparatus comprising:
a first set of denominator registers that store numbers representing denominator values;
a first set of multiplication circuitry that multiply pairs of register values and products of pairs of register values to produce combinations of products of the denominator values until all denominator values have been multiplied together;
a single division circuit that performs one division to invert the product resulting from multiplying all denominator values together;
a second set of multiplication circuitry that multiply combinations of products of the denominator values from the first multiplication circuitry with the inverted product from the division circuit; and
a second set of denominator registers that store the results of the second multiplications resulting in inversions of all of the numbers representing the denominators.
2. The apparatus of claim 1 , further comprising:
one or more numerator registers that store numbers representing numerator values for at least two divisions that should be performed and
one or more third set of multiplication circuitry that multiply the inverted denominators with the corresponding numerator values to produce division results.
3. The apparatus of claim 1 , further comprising:
a storage unit for storing exponents that are removed from the denominator numbers for later use; and
a third set of denominator registers that store the inversions of all the numbers representing the denominators with the exponents added back in.
4. A method for reducing central processing unit usage when inverting numbers, the method comprising:
receiving, via a set of denominator registers, a plurality of numbers to be inverted as denominator values;
grouping the denominator values into pairs;
multiplying, using multiplication circuitry, the pairs;
multiplying, using multiplication circuitry products of the pairs to produce combinations of products of the denominator values until all denominator values have been multiplied together;
inverting, using single division circuit, the product of all denominator values multiplied together using a single division; and
multiplying, using multiplication circuitry, combinations of products of the denominator values from the multiplications achieved before the division with the inverted product from the division to compute inversions of all the denominator values.
5. The method of claim 4 , further comprising:
receiving, via a numerator register, a plurality of numbers as numerator values that each correspond to one of the denominator values and
multiplying, using multiplication circuitry, each numerator with the corresponding inversion of the denominator value to produce division results.
6. The method of claim 4 , further comprising:
removing exponents from the denominator values and
restoring the exponents after the inversions of all the denominator values have been computed.