Reduction of Charging Induced Damage in Photolithography Wet Process
An approach is developed to use an acidic rinse to reduce charge during the lithographic process, and thereby eliminate the crystalline damage and associated yield loss associated with the accumulated charge. The crystalline damage has been found to occur for certain thicknesses of dielectric layers, and such damage is irreparable. A sparge can be used to dissolve carbon dioxide in water to provide a weak acidic rinse.
1 . A method comprising:
forming a dielectric layer over a substrate, the dielectric layer having a thickness;
patterning the dielectric layer, the patterning including using a developer having a pH greater than 7; and
applying a weak acidic rinse to the patterned dielectric layer.
2 . The method of claim 1 , wherein the dielectric layer comprises silicon dioxide.
3 . The method of claim 2 , further comprising:
removing the dielectric layer, wherein the dielectric layer is a sacrificial layer.
4 . The method of claim 1 , wherein the applying a weak acidic rinse includes adding an acidic component to a post develop de-ionized(DI) water rinse.
5 . The method of claim 1 , further comprising:
forming the weak acidic rinse by using a sparge to mix carbon dioxide with de-ionized. (DI) water.
6 . The method of claim 5 , wherein the water comprises incoming reclaimed water.
7 . The method of claim 5 , wherein the water comprises incoming municipal water.
8 . The method of claim 5 , wherein the water comprises incoming de-ionized (DI) water having small concentrations of non-volatile organic impurities.
9 . The method of claim 8 , wherein the non-volatile organic contaminant includes at least one organic compound, the at least one organic compound including carbamide, ethanol, propanal or isopropyl alcohol.
10 . The method of claim 1 , wherein the applying a weak acidic rinse comprises applying at least one of carbonic acid or carboxylic acid.
11 . The method of claim 1 , wherein the thickness lies within the range of 70 to 120 Angstroms.
12 . The method of claim 1 , further comprising:
overlaying a further layer in a region previously occupied by the removed dielectric layer.
13 . The method of claim 1 , further comprising:
overlaying a further layer in a region previously occupied by the removed dielectric layer; and
forming a pad over the further layer to thereby form a dielectric capacitor.
14 . The method of claim 13 , wherein the further layer comprises an oxide.
15 . The method of claim 1 , wherein the applying a weak acidic rinse is performed prior to applying a dry processing step.
16 . A lithographic structure, comprising:
a substrate;
a patterned dielectric layer formed on the substrate using a base developer solution, wherein a thickness of the patterned dielectric layer lies within a range of vulnerability to charge-induced damage, and wherein an interface between the substrate and the patterned dielectric layer is tree from the charge-induced damage.
17 . The lithographic structure of claim 16 , wherein the dielectric layer comprises silicon dioxide.
18 . The lithographic structure of claim 16 , wherein the dielectric layer comprises a sacrificial layer.
19 . The lithographic structure of claim 16 , wherein the substrate is a silicon wafer.
20 . The lithographic structure of claim 16 , wherein the range of vulnerability to charge-induced damage is 70 to 120 Angstroms.