IP Library Granted Patent US 9,251,063
Granted Patent B2
US 9,251,063 · App. 14/098,575 · Granted Feb 2, 2016

Storage system including a plurality of flash memory devices

Inventors: Shuji Nakamura (Kanagawa, JP); Kazuhisa Fujimoto (Tokyo, JP); Akira Fujibayashi (Kanagawa, JP)
Assignee: Hitachi, Ltd.
G06F12/0246G06F3/067G06F3/0626G06F3/0658G06F3/0688G06F12/0866G06F2212/2022G06F2212/263G06F2212/314Y02B60/1225
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Quick Facts
Patent No.
US 9,251,063
App. No.
14/098,575
Granted
Feb 2, 2016
Kind
B2
Abstract

A storage system including a storage device which includes media for storing data from a host computer, a medium controller for controlling the media, a plurality of channel controllers for connecting to the host computer through a channel and a cache memory for temporarily storing data from the host computer, wherein the media have a restriction on a number of writing times. The storage device includes a bus for directly transferring data from the medium controller to the channel controller.

Claims (64)

1. A storage system comprising:

a plurality of flash memory devices; and

a storage controller coupled to a computer, the storage controller including:

a processor configured to control read/write requests from the computer, and

a cache memory configured to store data temporarily,

wherein the processor is configured to:

according to a read request for first data from the computer, when the first data is not stored within the cache memory, transfer the first data requested by the read request from one of the plurality of flash memory devices to the computer without storing the first data in the cache memory, and

according to a write request from the computer, store second data requested by the write request in the cache memory.

2. The storage system according to claim 1 ,

wherein each of the plurality of flash memory devices includes a plurality of flash memory chips, and

wherein a wear leveling process is performed in the each of the plurality of flash memory devices.

3. The storage system according to claim 1 , wherein the plurality of flash memory devices is configured as a RAID (Redundant Array of Independent Disks) group.

4. The storage system according to claim 1 , wherein the cache memory is a volatile memory.

5. The storage system according to claim 1 , wherein the processor is further configured to:

according to the read request from the computer, determine whether the first data requested by the read request is stored in the one of the plurality of flash memory devices or not.

6. A storage system comprising:

a plurality of flash memory devices, each of the plurality of flash memory devices including a memory controller and a plurality of flash memory chips;

a device interface coupled to the plurality of flash memory devices;

a cache memory configured to store data temporarily;

a channel interface configured to receive a read request and a write request from a computer; and

a processor configured to:

when first data is not stored within the cache memory, transfer the first data, which is requested by the read request, stored in one of the plurality of flash memory devices to the computer via the device interface and the channel interface without storing the first data in the cache memory, and

store second data, which is requested by the write request, in the cache memory.

7. The storage system according to claim 6 , wherein the memory controller performs a wear leveling process for the plurality of flash memory chips.

8. The storage system according to claim 6 , wherein the plurality of flash memory devices are configured as a RAID (Redundant Array of Independent Disks) group.

9. The storage system according to claim 6 , wherein the processor is further configured to:

according to the read request from the computer, determine whether the first data requested by the read request is stored in the one of the plurality of flash memory devices or not.

10. A storage system comprising:

a plurality of flash memory devices;

a plurality of hard disk devices; and

a storage controller coupled to a computer, the storage controller including:

a processor configured to control read/write requests from the computer, and

a cache memory configured to store data temporarily,

wherein the processor is configured to:

according to a read request from the computer, determine whether target data of the read request is stored within any of the plurality of flash memory devices or any of the plurality of hard disk devices, when the target data of the read request is not stored within the cache memory, and

transfer the target data from one of the plurality of flash memory devices to the computer without storing the target data in the cache memory when the target data is stored in one of the plurality of flash memory devices and not stored within the cache memory.

11. The storage system according to claim 10 ,

wherein each of the plurality of flash memory devices includes a plurality of flash memory chips, and

wherein a wear leveling process is performed in the each of the plurality of flash memory devices.

12. The storage system according to claim 10 , wherein the plurality of flash memory devices is configured as a RAID (Redundant Array of Independent Disks) group.

13. The storage system according to claim 10 , wherein the cache memory is a volatile memory.

14. A storage system according to claim 10 , wherein the processor is further configured to:

transfer the target data from one of the plurality of hard disk devices to the computer via the cache memory when the target data is stored in one of the plurality of hard disk devices.

15. A storage system comprising:

a plurality of flash memory devices, each of the plurality of flash memory devices including a memory controller and a plurality of flash memory chips;

a device interface coupled to the plurality of flash memory devices;

a cache memory configured to store data temporarily;

a channel interface configured to receive a read request and a write request from a computer; and

a processor configured to determine whether target data of the read request is stored within any of the plurality of flash memory devices or not, and when the target data is not stored within the cache memory, transfer the target data stored within one of the plurality of flash memory devices to the computer via the device interface and the channel interface without storing the data in the cache memory.

16. The storage system according to claim 15 , wherein the memory controller performs a wear leveling process for the plurality of flash memory chips.

17. The storage system according to claim 15 , wherein the plurality of flash memory devices are configured as a RAID (Redundant Array of Independent Disks) group.

18. A storage system comprising:

a plurality of flash memory devices; and

a storage controller coupled to a computer, the storage controller including:

a processor configured to control read/write requests from the computer,

a cache memory configured to store data temporarily, and

a control memory configured to store information for managing data stored within the cache memory,

wherein the processor is configured to determine whether target data of a read request from the computer is stored within any of the plurality of flash memory devices or not, according to the request from the computer, and

wherein when target data of the read request is not stored within the cache memory and is stored in one of the plurality of flash memory devices, the processor transfers the target data stored within the one of the plurality of flash memory devices to the computer without accessing the control memory in a process of transferring the target data.

19. The storage system according to claim 18 ,

wherein each of the plurality of flash memory devices includes a plurality of flash memory chips, and

wherein a wear leveling process is performed in the each of the plurality of flash memory devices.

20. The storage system according to claim 18 , wherein the plurality of flash memory devices is configured as a RAID (Redundant Array of Independent Disks) group.

21. The storage system according to claim 18 , wherein each of the cache memory and the control memory is a volatile memory.

Assignments (1)
COMPANY SPLIT Recorded Aug 20, 2024
From: HITACHI, LTD.
To: HITACHI VANTARA, LTD.
Reel/Frame 069518/0761 →
Priority Claims (1)
JP 2005-252989 · Sep 1, 2005 · national
Continuity (4)
Continuation 13688447 · Nov 29, 2012
Continuation 12250694 · Oct 14, 2008
Continuation 11247161 · Oct 12, 2005
Related Publication 20140095776A1 · Apr 3, 2014