Method and apparatus for staggered start-up of a predefined, random or dynamic number of flash memory devices

1. An apparatus, comprising:

a plurality of memory devices, wherein each memory device of the plurality of memory devices is powered by a power supply,

wherein, upon a voltage of the power supply reaching a pre-determined level, a first memory device of the plurality of memory devices is configured to:

receive a first set of instructions;

execute a first portion of the first set of instructions; and

after executing the first portion of the first set of instructions, execute a second portion of the first set of instructions after a first delay period,

and wherein, upon the power supply voltage reaching the pre-determined level, a second memory device of the plurality of memory devices is configured to:

receive a second set of instructions;

execute a first portion of the second set of instructions; and

after executing the first portion of the second set of instructions, execute a second portion of the second set of instructions after a second delay period, the second delay period being different than the first delay period.

2. The apparatus of claim 1 , wherein each memory device of the plurality of memory devices further includes a random access memory, and the first set of instructions received by the first memory device are loaded into the random access memory of the first memory device, and the second set of instructions received by the second memory device are loaded into the random access memory of the second memory device.

3. The apparatus of claim 1 , further comprising at least one countdown timer configured to provide the first delay period and the second delay period.

4. The apparatus of claim 3 , wherein each memory device of the plurality of memory devices includes a plurality of memory cells including a trim sector; wherein the trim sector stores a bad sector map, a program verify point, and an erase verify point; wherein the trim sector of the first memory device includes a script that causes the first memory device to employ the countdown timer to wait for the first delay period after executing the first portion of the first set of instructions for the first memory device; and wherein the trim sector of the second memory device includes a script that causes the second memory device to employ the countdown timer to wait for the second delay period after executing the first portion of the second set of instructions for the second memory device.

5. The apparatus of claim 1 , wherein, each of one or more additional memory devices of the plurality of memory devices are configured to:

execute a first portion of a corresponding set of received instructions, and

after executing the first portion of the corresponding set of instructions, each of the one or more additional memory devices executes a second portion of the corresponding set of instructions after a corresponding delay period, the corresponding delay period being different for each of the one or more additional memory devices.

6. The apparatus of claim 1 , wherein the plurality of memory devices are arranged in columns, and wherein the first memory device is located in a different column than the second memory device.

7. The apparatus of claim 1 , wherein each memory device of the plurality of memory devices includes a controller component, a decoder component, and a plurality of memory cells.

8. The apparatus of claim 7 , wherein each of the controller components includes means for controlling accesses to the memory cells, wherein each of the decoder components includes means for decoding, or wherein each of the memory cells includes means for storing at least one bit.

9. A method in response to a power supply voltage of a power supply reaching a pre-determined level, comprising:

receiving a first set of instructions at a first memory device coupled to the power supply and a second set of instructions at a second memory device coupled to the power supply;

executing, by the first memory device, a first portion of the first set of instructions;

executing, by the second memory device, a first portion of the second set of instructions;

after executing the first portion of the first set of instructions, executing, by the first memory device, a second portion of the first set of instructions after a first delay period; and

after executing the first portion of the second set of instructions, executing, by the second memory device, a second portion of the second set of instructions after a second delay period, the first delay period being different than the second delay period.

10. A tangible processor-readable medium having processor-executable code encoded therein, which, upon execution by one or more processors, causes the one or more processors to perform operations upon a power supply voltage reaching a pre-determined level, the operations comprising:

receiving a first set of instructions at a first memory device and a second set of instructions at a second memory device;

executing a first portion of the first set of instructions;

executing a first portion of the second set of instructions;

after executing the first portion of the first set of instructions, executing a second portion of the first set of instructions after a first delay period; and

after executing the first portion of the second set of instructions, executing a second portion of the second set of instructions after a second delay period, the first delay period being different than the second delay period.