Integrated circuit for controlling radio communication process
View Patent ↗Provided is a radio communication device which can make Acknowledgement (ACK) reception quality and Negative Acknowledgement (NACK) reception quality to be equal to each other. The device includes: a scrambling unit ( 214 ) which multiplies a response signal after modulated, by a scrambling code “1” or “e −j(π/2) ” so as to rotate a constellation for each of response signals on a cyclic shift axis; a spread unit ( 215 ) which performs a primary spread of the response signal by using a Zero Auto Correlation (ZAC) sequence set by a control unit ( 209 ); and a spread unit ( 218 ) which performs a secondary spread of the response signal after subjected to the primary spread, by using a block-wise spread code sequence set by the control unit ( 209 ).
1. An integrated circuit for controlling a process comprising:
transmitting data to a mobile station and transmitting, to the mobile station, control information related to the data on a control channel element (CCE); and
receiving, from the mobile station, an ACK or NACK symbol that is multiplied with an orthogonal sequence, which is one of plural orthogonal sequences, and with a sequence defined by a cyclic shift value, which is one of plural cyclic shift values and which is associated with the orthogonal sequence, the ACK or NACK symbol being scrambled by 1 or e j(π/2) ,
wherein:
the orthogonal sequence, with which the ACK or NACK symbol is multiplied, and the cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, are associated with a CCE number of said CCE; and
the ACK or NACK symbol is scrambled by 1 when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of two cyclic shift values that are associated with one of the plural orthogonal sequences and that are next to each other at a set interval, and is scrambled by e j(π/2) when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is the other of the two cyclic shift values.
2. The integrated circuit according to claim 1 , wherein the control information includes resource assignment information of the data.
3. The integrated circuit according to claim 1 , wherein the control information is transmitted on one or a plurality of the CCE(s) with consecutive CCE number(s), and the orthogonal sequence, with which the ACK or NACK symbol is multiplied, and the cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, are associated with the first CCE number of the CCE(s) used for transmission of the control information.
4. The integrated circuit according to claim 1 , wherein the set interval is a minimum difference between plural cyclic shift values that are associated with one of the plural orthogonal sequences.
5. The integrated circuit according to claim 1 , wherein the set interval is a difference between two cyclic shift values, which are closest to each other among plural cyclic shift values that are associated with one of the plural orthogonal sequences.
6. The integrated circuit according to claim 1 , wherein:
an index of resource used for transmission of the ACK or NACK symbol by the mobile station is associated with the CCE number;
the cyclic shift value and the orthogonal sequence used by the mobile station are determined from the index; and
the ACK or NACK symbol is multiplied with a sequence, which is defined by the determined cyclic shift value, and with the determined orthogonal sequence.
7. The integrated circuit according to claim 1 , wherein plural cyclic shift values, each of which is incremented by the set interval, are associated with one of the plural orthogonal sequences.
8. The integrated circuit according to claim 1 , wherein:
plural cyclic shift values, each of which is incremented by the set interval, are associated with one of the plural orthogonal sequences; and
1 and e j(π/2) are selected alternately each time a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is incremented by the set interval, and the ACK or NACK symbol is scrambled by the selected 1 or e j(π/2) .
9. The integrated circuit according to claim 1 , wherein:
plural first cyclic shift values, which are not next to each other at the set interval, and plural second cyclic shift values, which are not next to each other at the set interval and which are different from the plural first cyclic shift values, are both associated with one of the plural orthogonal sequences; and
the ACK or NACK symbol is scrambled by 1 when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of the plural first cyclic shift values, and is scrambled by e j(π/2) when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of the plural second cyclic shift values.
10. An integrated circuit for controlling a process comprising:
transmitting data to a mobile station and transmitting, to the mobile station, control information related to the data on a control channel element (CCE); and
receiving, from the mobile station, an ACK or NACK symbol that is multiplied with an orthogonal sequence, which is one of three orthogonal sequences, and with a sequence defined by a cyclic shift value, which is one of twelve cyclic shift values and which is associated with the orthogonal sequence, the ACK or NACK symbol being scrambled by 1 or e j(π/2) ,
wherein:
the orthogonal sequence, with which the ACK or NACK symbol is multiplied, and the cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, are associated with a CCE number of said CCE;
the twelve cyclic shift values are represented by consecutive numbers #0 to #11 in the direction in which a cyclic shift value is incremented by a set value;
six cyclic shift values represented by #0, #2, #4, #6, #8 and #10 are associated with one of the three orthogonal sequences; and
the ACK or NACK symbol is scrambled by one of 1 and e j(π/2) when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of cyclic shift values represented by #0, #4, and #8, and is scrambled by the other of 1 and e j(π/2) when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of cyclic shift values represented by #2, #6, and #10.
11. The integrated circuit according to claim 10 , wherein:
six cyclic shift values represented by #1, #3, #5, #7, #9 and #11 are associated with one of the other two of the three orthogonal sequences; and
the ACK or NACK symbol is scrambled by one of 1 and e j(π/2) when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of cyclic shift values represented by #1, #5, and #9, and is scrambled by the other of 1 and e j(π/2) when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of cyclic shift values represented by #3, #7, and #11.
12. The integrated circuit according to claim 10 , wherein:
six cyclic shift values represented by #1, #3, #5, #7, #9 and #11 are associated with one of the other two of the three orthogonal sequences; and
the ACK or NACK symbol is scrambled by one of 1 and e j(π/2) when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of cyclic shift values represented by #0, #1, #4, #5, #8 and #9, and is scrambled by the other of 1 and e j(π/2) when a cyclic shift value that defines the sequence, with which the ACK or NACK symbol is multiplied, is one of cyclic shift values represented by #2, #3, #6, #7, #10 and #11.