Solar cell
A solar cell has a condenser lens and a solar cell element, the solar cell element including an n-type InGaAs layer, an n-type GaAs layer, an n-type InGaP layer, the first InGaAs peripheral part having a thickness (d2), and a width (w2), the second InGaAs peripheral part having a thickness (d3), and a width (w3), the first GaAs peripheral part having a thickness (d5), and a width (w4), the second GaAs peripheral part a thickness (d6), and a width (w5), the first InGaP peripheral part having a thickness (d8), and a width (w6), the second InGaP peripheral part having a thickness (d9), and a width (w7), the following inequation set being satisfied: 1 nm≤(d2, d3, d5, and d6)≤4 nm, 1 nm≤(d8 and d9)≤5 nm, 100 nm≤(w2, w3, w4, w5, w6, and w7), the InGaAs center part having a thickness (w1), a window layer has a range S irradiated by sunlight having a width (w8); w8≤w1.
1. A method for generating an electric power using a solar cell, the method comprising:
(a) preparing the solar cell comprising a condenser lens and a solar cell element;
wherein the solar cell element comprises an n-type InGaAs layer, a p-type InGaAs layer, an n-type GaAs layer, a p-type GaAs layer-, an n-type InGaP layer, a p-type InGaP layer, a first tunnel junction layer, a second tunnel junction layer, a window layer, an n-side electrode, and a p-side electrode;
Z direction is a normal line direction of the p-type InGaAs layer;
X direction is perpendicular to the Z direction;
the n-type InGaAs layer, the p-type InGaAs layer, the first tunnel junction layer, the n-type GaAs layer, the p-type GaAs layer, the second tunnel junction layer, the n-type InGaP layer, the p-type InGaP layer, and the window layer are stacked in this order along the Z direction;
the n-side electrode is connected electrically to the n-type InGaAs layer;
the p-side electrode is connected electrically to the p-type InGaP layer;
the n-type InGaAs layer is divided into an InGaAs center part, a first InGaAs peripheral part, and a second InGaAs peripheral part;
the InGaAs center part is interposed between the first InGaAs peripheral part and the second InGaAs peripheral part along the X direction;
the first InGaAs peripheral part and the second InGaAs peripheral part have a shape of a layer;
the n-type GaAs layer is divided into a GaAs center part, a first GaAs peripheral part, and a second GaAs peripheral part;
the GaAs center part is interposed between the first GaAs peripheral part and the second GaAs peripheral part along the X direction;
the first GaAs peripheral part and the second GaAs peripheral part have a shape of a layer;
the n-type InGaP layer is divided into an InGaP center part, a first InGaP peripheral part, and a second InGaP peripheral part;
the InGaP center part is interposed between the first InGaP peripheral part and the second InGaP peripheral part along the X direction;
the first InGaP peripheral part and the second InGaP peripheral part have a shape of a layer;
the following inequation set (I) is satisfied;
(I)
d2<d1,
d3<d1,
1 nanometer≤d2≤4 nanometers,
1 nanometer≤d3≤4 nanometers,
d5<d4,
d6<d4,
1 nanometer≤d5≤4 nanometers,
1 nanometer≤d6≤4 nanometers,
d8<d7,
d9<d7,
1 nanometer≤d8≤5 nanometers,
1 nanometer≤d9≤5 nanometers,
100 nanometers≤w2,
100 nanometers≤w3,
100 nanometers≤w4,
100 nanometers≤w5,
100 nanometers≤w6, and
100 nanometers≤w7
d1 represents a thickness of the InGaAs center part along the Z direction;
d2 represents a thickness of the first InGaAs peripheral part along the Z direction;
d3 represents a thickness of the second InGaAs peripheral part along the Z direction;
d4 represents a thickness of the GaAs center part along the Z direction;
d5 represents a thickness of the first GaAs peripheral part along the Z direction;
d6 represents a thickness of the second GaAs peripheral part along the Z direction;
d7 represents a thickness of the InGaP center part along the Z direction;
d8 represents a thickness of the first InGaP peripheral part along the Z direction;
d9 represents a thickness of the second InGaP peripheral part along the Z direction;
w2 represents a width of the first InGaAs peripheral part along the X direction;
w3 represents a width of the second InGaAs peripheral part along the X direction;
w4 represents a width of the first GaAs peripheral part along the X direction,
w5 represents a width of the second GaAs peripheral part along the X direction;
w6 represents a width of the first InGaP peripheral part along the X direction; and
w7 represents a width of the second InGaP peripheral part along the X direction;
(b) irradiating a region S which is included in the surface of the window layer through the condenser lens with light in such a manner that the following inequation (II) is satisfied so as to generate a voltage difference between the n-side electrode and the p-side electrode;
w8≤w1 (II)
where, w1 represents a width of the InGaAs center part along the X direction;
w8 represents a width of the range S along the X direction when viewed in the cross-sectional view which includes the Z direction; and the first center part overlaps the region S when viewed from the Z-direction.
2. The method according to claim 1 , wherein the following equation is satisfied:
w 1+ w 2+ w 3+ w 4+ w 5+ w 6+ w 7= w 8+ w 9+ w 10
where, w9 and the width w10 represent widths of portions of the window layer which are not irradiated with the light.
3. The method according to claim 1 , wherein sides of the n-type InGaAs layer, the p-type InGaAs layer, the first tunnel junction layer, the n-type GaAs layer, the p-type GaAs layer, the second tunnel junction layer, the n-type InGaP layer, the p-type InGaP layer and the p-type window layer are covered with an insulation layer.
4. A solar cell comprising a condenser lens and a solar cell element,
wherein the solar cell element comprises an n-type InGaAs layer, a p-type InGaAs layer, an n-type GaAs layer, a p-type GaAs layer, an n-type InGaP layer, a p-type InGaP layer, a first tunnel junction layer, a second tunnel junction layer, a window layer, an n-side electrode, and a p-side electrode;
Z direction is a normal line direction of the p-type InGaAs layer;
X direction is perpendicular to the Z direction;
the n-type InGaAs layer, the p-type InGaAs layer, the first tunnel junction layer, the n-type GaAs layer, the p-type GaAs layer, the second tunnel junction layer, the n-type InGaP layer, the p-type InGaP layer, and the window layer are stacked in this order along the Z direction;
the n-side electrode is connected electrically to the n-type InGaAs layer;
the p-side electrode is connected electrically to the p-type InGaP layer;
the n-type InGaAs layer is divided into an InGaAs center part, a first InGaAs peripheral part, and a second InGaAs peripheral part;
the InGaAs center part is interposed between the first InGaAs peripheral part and the second InGaAs peripheral part along the X direction;
the first InGaAs peripheral part and the second InGaAs peripheral part have a shape of a layer;
the n-type GaAs layer is divided into a GaAs center part, a first GaAs peripheral part, and a second GaAs peripheral part;
the GaAs center part is interposed between the first GaAs peripheral part and the second GaAs peripheral part along the X direction;
the first GaAs peripheral part and the second GaAs peripheral part have a shape of a layer;
the n-type InGaP layer is divided into an InGaP center part, a first InGaP peripheral part, and a second InGaP peripheral part;
the InGaP center part is interposed between the first InGaP peripheral part and the second InGaP peripheral part along the X direction;
the first InGaP peripheral part and the second InGaP peripheral part have a shape of a layer;
the following inequation set (I) is satisfied;
(I)
d2<d1,
d3<d1,
1 nanometer≤d2≤4 nanometers,
1 nanometer≤d3≤4 nanometers,
d5<d4,
d6<d4,
1 nanometer≤d5≤4 nanometers,
1 nanometer≤d6≤4 nanometers,
d8<d7,
d9<d7,
1 nanometer≤d8≤5 nanometers,
1 nanometer≤d9≤5 nanometers,
100 nanometers≤w2,
100 nanometers≤w3,
100 nanometers≤w4,
100 nanometers≤w5,
100 nanometers≤w6, and
100 nanometers≤w7
d1 represents a thickness of the InGaAs center part along the Z direction;
d2 represents a thickness of the first InGaAs peripheral part along the Z direction;
d3 represents a thickness of the second InGaAs peripheral part along the Z direction;
d4 represents a thickness of the GaAs center part along the Z direction;
d5 represents a thickness of the first GaAs peripheral part along the Z direction;
d6 represents a thickness of the second GaAs peripheral part along the Z direction;
d7 represents a thickness of the InGaP center part along the Z direction;
d8 represents a thickness of the first InGaP peripheral part along the Z direction;
d9 represents a thickness of the second InGaP peripheral part along the Z direction;
w2 represents a width of the first InGaAs peripheral part along the X direction;
w3 represents a width of the second InGaAs peripheral part along the X direction;
w4 represents a width of the first GaAs peripheral part along the X direction,
w5 represents a width of the second GaAs peripheral part along the X direction;
w6 represents a width of the first InGaP peripheral part along the X direction; and
w7 represents a width of the second InGaP peripheral part along the X direction.