Decimation filter
View Patent ↗A system includes a decimation module having an adjustable decimation rate and a filter module responsive to the decimation module. A digital phase lock loop is operable to control a decimation rate of the decimation module. The decimation module is a cascade integrator comb decimation module.
1. A system comprising:
a decimation module having an adjustable decimation rate, wherein the decimation module includes a cascade integrator comb decimation module;
a filter module responsive to the decimation module;
a delta sigma modulator to receive an analog input signal, the delta sigma modulator responsive to a first clock;
a bus interface module responsive to the filter module, the bus interface module responsive to a second clock; and
a digital phase lock loop configured to measure a difference between a rate of the first clock and a rate of the second clock and to control the adjustable decimation rate of the decimation module based on the measured difference between the rate of the first clock and the rate of the second clock, wherein the first clock comprises an on-chip clock and the second clock is based on an external clock.
2. The system of claim 1 , wherein the filter module includes a plurality of finite impulse response filters.
3. The system of claim 1 , wherein the adjustable decimation rate includes a non-integer portion to allow decimation at a non-integer rate.
4. The system of claim 1 , wherein the digital phase lock loop is configured to control the adjustable decimation rate of the decimation module via an adjustable rate decimation signal.
5. The system of claim 4 , wherein the decimation module includes an output adjustment module, a variable rate down sampling module, and an adder.
6. The system of claim 5 , wherein the output adjustment module is configured to add an adjustment factor to an output of the variable rate down sampling module, and wherein the adjustment factor is based on a change in the adjustable decimation rate multiplied by an output of the adder.
7. A method comprising:
receiving an analog input at a delta sigma modulator, the delta sigma modulator responsive to a first clock;
digitizing the analog input to yield a digital signal;
providing the digital signal to a cascade integrator comb (CIC) decimation filter;
measuring, by a digital phase lock loop (PLL), a difference between a first clock rate of the first clock and a second clock rate of a second clock;
receiving, at the CIC decimation filter, a control signal from the digital PLL, wherein the control signal is based on the measured difference;
in response to the control signal, adjusting a decimation rate of the CIC decimation filter;
decimating the digital signal based on the decimation rate of the CIC decimation filter;
filtering the decimated digital signal a filter module; and
providing the filtered decimated digital signal to a bus interface module, the bus interface module responsive to the second clock, wherein the first clock comprises an on-chip clock and the second clock is based on an external clock.
8. The method of claim 7 , further comprising further adjusting the decimation rate of the CIC decimation filter in response to a change in one or more of the first clock rate of the first clock and the second clock rate of the second clock.
9. The method of claim 7 , wherein the filter module comprises a plurality of finite impulse response (FIR) filters, and further comprising filtering the decimated digital signal by the plurality of FIR filters.
10. The method of claim 7 , wherein the decimation rate is a non-integer rate.
11. The method of claim 7 , wherein the CIC decimation filter includes a variable rate down sampling module and an adder.
12. The method of claim 11 , further comprising adding an adjustment factor to an output of the variable rate down sampling module, wherein the adjustment factor is based on a change in the control signal multiplied by an output of the adder.
13. An apparatus comprising:
means for decimating digital signals, wherein the means for decimating has an adjustable decimation rate, wherein the means for decimating includes a cascade integrator comb (CIC) decimation filter;
means for filtering digital signals, wherein the means for filtering is coupled to the means for decimating;
a delta sigma modulator configured to receive an analog input signal, the delta sigma modulator responsive to a first clock;
a bus interface module responsive to the means for filtering, the bus interface module responsive to a second clock; and
a digital phase lock loop (PLL), wherein the digital PLL is configured to measure a difference between a rate of the first clock and a rate of the second clock and to control a decimation rate of the means for decimating based on the measured difference between the rate of the first clock and the rate of the second clock, wherein the first clock comprises on an on-chip clock and the second clock is based on an external clock.
14. The apparatus of claim 13 , wherein the digital PLL controls the decimation rate of the means for decimating via a control signal.
15. The apparatus of claim 14 , wherein the means for decimating includes an output adjustment module, a variable rate down sampling module, and an adder.
16. The apparatus of claim 15 , wherein the output adjustment module is configured to add an adjustment factor to an output of the variable rate down sampling module, and wherein the adjustment factor is based on a change in the control signal multiplied by an output of the adder.