Compliant interconnects in wafers

1. A method of fabricating a microelectronic unit, comprising:

removing material from a substrate having a CTE less than 10 ppm/° C. to form a hole extending from a major surface of the substrate to a second surface opposite the major surface;

forming an electrically conductive element having a joining portion extending above and supported on the major surface, an anchor portion fixed relative to the substrate, and a connecting portion extending downwardly from the joining portion to the anchor portion, a surface of the connecting portion having a contour conforming to a contour of an inner surface of the hole;

removing material supporting at least a joining portion of the conductive element from the major surface to form a recess such that the joining portion at least partially overlies the recess, and such that the contour of the surface of the connecting portion does not conform to a contour of an inner surface of the recess; and

depositing a material within the recess having a modulus of elasticity less than 10 GPa,

wherein the joining portion is at least partially exposed at the major surface of the substrate for connection to a component external to the microelectronic unit.

2. The method as claimed in claim 1 , wherein the substrate has a CTE less than 7 ppm/° C.

3. The method as claimed in claim 1 , further comprising, before the step of forming the conductive element, forming a conductive via extending within the hole and extending towards the second surface, such that the step of forming the conductive element electrically couples the conductive element with the conductive via.

4. The method as claimed in claim 1 , wherein the step of forming the conductive element is performed such that the joining portion is non-centered relative to the connecting portion.

5. The method as claimed in claim 1 , wherein the step of forming the conductive element is performed such that the joining portion is disposed substantially parallel to the major surface.

6. The method as claimed in claim 1 , wherein the substrate consists essentially of one material selected from the group consisting of: semiconductor, glass, and ceramic.

7. The method as claimed in claim 1 , wherein the substrate includes a plurality of active semiconductor devices, and the step of forming the conductive element electrically connects the conductive element with at least one of the plurality of active semiconductor devices.

8. The method as claimed in claim 1 , wherein the step of forming the conductive element is performed such that the joining portion defines an internal aperture.

9. The method as claimed in claim 8 , wherein the step of forming the conductive element is performed such that the aperture extends through the joining portion into the connecting portion.

10. The method as claimed in claim 9 , further comprising depositing a dielectric material into at least a portion of the aperture.

11. The method as claimed in claim 1 , wherein the step of removing material from the substrate to form a hole includes forming a first opening extending from the major surface towards the second surface and a second opening extending from the first opening to the second surface, wherein inner surfaces of the first and second openings extend in first and second directions relative to the major surface, respectively, to define a substantial angle.

12. A method of fabricating a stacked assembly including at least first and second microelectronic units, the first microelectronic unit being fabricated as claimed in claim 1 , further comprising the step of electrically connecting the substrate of the first microelectronic unit to a substrate of the second microelectronic unit.