IP Library Granted Patent US 10,025,120
Granted Patent B2
US 10,025,120 · App. 14/105,527 · Granted Jul 17, 2018

Method and system for a low parasitic silicon high-speed phase modulator having raised fingers perpendicular to the PN junction

Inventors: Ali Ayazi (Carlsbad, CA); Gianlorenzo Masini (Carlsbad, CA); Subal Sahni (La Jolla, CA); Attila Mekis (Carlsbad, CA); Thierry Pinguet (Arlington, WA)
Assignee: Luxtera, Inc.
G02F1/025G02F1/2257G02F2001/212G02F2201/06G02F2202/105
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Quick Facts
Patent No.
US 10,025,120
App. No.
14/105,527
Granted
Jul 17, 2018
Kind
B2
Abstract

Methods and systems for a low-parasitic silicon high-speed phase modulator are disclosed and may include fabricating an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer may be on an oxide layer and the oxide layer may be on a silicon substrate. The PN junction waveguide may have p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide, and portions of the p-doped and n-doped regions may be removed. Contacts may be formed on remaining portions of the p-doped and n-doped regions. Portions of the p-doped and n-doped regions may be removed symmetrically about the PN junction waveguide. Portions of the p-doped and n-doped regions may be removed in a staggered fashion along the length of the PN junction waveguide. Etch transition features may be removed along the p-doped and n-doped regions.

Claims (32)

1. A method for a semiconductor device, the method comprising:

fabricating an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer is on an oxide layer and the oxide layer is on a silicon substrate, said PN junction waveguide having p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide with only p-doping on a first of said opposite sides and only n-doping on a second of said opposite sides;

removing first portions of the p-doped and n-doped regions thereby forming the PN junction waveguide;

removing second portions of the p-doped and n-doped regions intermittently along a length of the PN junction waveguide such that raised fingers of p-doped and n-doped regions are formed along said PN junction waveguide, wherein a major axis of said raised fingers is perpendicular to said PN junction waveguide and a minor axis of said raised fingers is parallel to said PN junction waveguide; and

forming contacts to said fingers of p-doped and n-doped regions.

2. The method according to claim 1 , comprising removing the second portions of the p-doped and n-doped regions symmetrically about the PN junction waveguide.

3. The method according to claim 1 , comprising removing the second portions of the p-doped and n-doped regions in a staggered fashion along the length of the PN junction waveguide.

4. The method according to claim 1 , comprising removing etch transition features along the p-doped and n-doped regions, wherein the etch transition features provide a transition between deep etched and shallow etched features in the optical phase modulator.

5. The method according to claim 1 , wherein the silicon layer, oxide layer, and silicon substrate comprise a silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) wafer.

6. The method according to claim 1 , comprising reducing a parasitic capacitance of the optical phase modulator by the removing of the second portions of the p-doped and n-doped regions.

7. The method according to claim 1 , wherein the optical phase modulator is integrated in an optical transceiver formed on the silicon substrate.

8. The method according to claim 1 , wherein the remaining portions of the p-doped and n-doped regions comprise fingers for forming contacts that are staggered on opposite sides along the length of the PN junction waveguide.

9. The method according to claim 1 , comprising removing the second portions of the p-doped and n-doped regions down to the oxide layer on the silicon substrate.

10. The method according to claim 1 , wherein the optical phase modulator is integrated in a Mach-Zehnder interferometer modulator.

11. A system for communication, the system comprising:

an optical phase modulator that comprises a PN junction waveguide formed in a silicon layer, wherein the silicon layer is on an oxide layer and the oxide layer is on a silicon substrate;

first p-doped and n-doped regions on opposite sides along a length forming the PN junction waveguide with only p-doping on a first of said opposite sides and only n-doping on a second of said opposite sides;

regions where the p-doped and n-doped regions have been intermittently removed along the length of the PN junction waveguide such that raised fingers of p-doped and n-doped regions are formed along said PN junction waveguide, wherein a major axis of said raised fingers is perpendicular to said PN junction waveguide and a minor axis of said raised fingers is parallel to said PN junction waveguide; and

contacts formed on said fingers of p-doped and n-doped regions.

12. The system according to claim 11 , wherein portions of the p-doped and n-doped regions are removed symmetrically about the PN junction waveguide.

13. The system according to claim 11 , wherein portions of the p-doped and n-doped regions are removed in a staggered fashion along the length of the PN junction waveguide.

14. The system according to claim 11 , wherein etch transition features are removed along the p-doped and n-doped regions, wherein the etch transition features provide a transition between deep etched and shallow etched features in the optical phase modulator.

15. The system according to claim 14 , wherein the remaining portions of the p-doped and n-doped regions comprise fingers where contacts are formed that are staggered on opposite sides along the length of the PN junction waveguide.

16. The system according to claim 11 , wherein the silicon layer, oxide layer, and silicon substrate comprise a silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) wafer.

17. The system according to claim 11 , wherein the optical phase modulator is integrated in an optical transceiver formed on the silicon substrate.

18. The system according to claim 11 , wherein portions of the p-doped and n-doped regions are removed down to the oxide layer on the silicon substrate.

19. The system according to claim 11 , wherein the optical phase modulator is integrated in a Mach-Zehnder interferometer modulator.

20. A system for communication, the system comprising:

a Mach-Zehnder optical modulator that comprises a PN junction waveguide formed in a silicon layer on an oxide layer, wherein the silicon layer and the oxide layer are part of a silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) substrate;

p-doped and n-doped regions on opposite sides along a length of the PN junction waveguide with only p-doping on a first of said opposite sides and only n-doping on a second of said opposite sides;

regions where the p-doped and n-doped regions have been removed in an alternating fashion along the length of the PN junction waveguide such that raised fingers of p-doped and n-doped regions are formed along said PN junction waveguide, wherein a major axis of said raised fingers is perpendicular to said PN junction waveguide and a minor axis of said raised fingers is parallel to said PN junction waveguide; and

contacts formed on said fingers of p-doped and n-doped regions.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNOR'S NAME PREVIOUSLY RECORDED AT REEL: 058979 FRAME: 0027. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 24, 2022
From: LUXTERA LLC
To: CISCO TECHNOLOGY, INC.
Reel/Frame 059496/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2022
From: CISCO SYSTEMS, INC.
To: CISCO TECHNOLOGY, INC.
Reel/Frame 058979/0027 →
RELEASE OF SECURITY INTEREST Recorded Dec 24, 2020
From: SILICON VALLEY BANK
To: LUXTERA, LLC
Reel/Frame 054855/0838 →
CHANGE OF NAME Recorded Feb 6, 2020
From: LUXTERA, INC.
To: LUXTERA LLC
Reel/Frame 052019/0811 →
SECURITY INTEREST Recorded Mar 29, 2017
From: LUXTERA, INC.
To: SILICON VALLEY BANK
Reel/Frame 042109/0140 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 18, 2015
From: AYAZI, ALI; MASINI, GIANLORENZO; SAHNI, SUBAL; MEKIS, ATTILA; PINGUET, THIERRY
To: LUXTERA, INC.
Reel/Frame 035036/0008 →
Continuity (2)
Provisional Application 61797697 · Dec 13, 2012
Related Publication 20150316793A1 · Nov 5, 2015
Cited By (2)
US 12,292,624 US 12,411,366