SYSTEMS AND METHODS FOR DEFEATING MALWARE WITH RANDOMIZED OPCODE VALUES
A computer processor includes a first instruction set and a second instruction set. The computer processor further includes a translator. The translator translates the first instruction set into the second instruction set. The computer processor is configured to execute operations using only the second complete instruction set.
1 . A computer processor comprising:
a first complete instruction set; and
a translator to translate the first complete instruction set into a second complete instruction set, the computer processor configured to execute operations using only the second complete instruction set.
2 . The computer processor of claim 1 , wherein the first complete instruction set is native to the computer processor; and wherein the second complete instruction set is not native to the computer processor.
3 . The computer processor of claim 1 , wherein a translation from the first complete instruction set to the second complete instruction set occurs at boot up of the computer processor.
4 . The computer processor of claim 1 , wherein a translation from the first complete instruction set to the second complete instruction set occurs in connection with loading program code for a process that is executed by the computer processor.
5 . The computer processor of claim 4 , wherein the process executes using the second complete instruction set; and wherein other processes in the computer processor execute using the first complete instruction set.
6 . The computer processor of claim 1 , wherein the translator uses a translate table that maps each instruction in the first complete instruction set to a corresponding instruction of substantially equivalent function in the second complete instructions set; and wherein the byte code for each instruction in the first complete instruction set is different than the byte code for the corresponding instruction of substantially equivalent function in the second complete instruction set.
7 . The computer processor of claim 1 , wherein the translator generates a randomized second complete instruction set.
8 . The computer processor of claim 7 , wherein the computer processor uses a translation seed to generate the randomized second complete instruction set.
9 . The computer processor of claim 8 , wherein the translation seed is stored in a secure location in a kernel of an operating system.
10 . The computer processor of claim 1 , wherein the computer is operable to transfer a process and a translate table associated with the process or a translation seed associated with the process to a second computer processor.
11 . The computer processor of claim 1 , wherein the translator generates a globally unique second complete instruction set in relation to one or more of a particular computer processor, a particular instantiation of an operating system, a particular process executing in the computer processor, and a particular thread associated with the particular process.
12 . A process comprising:
maintaining a first complete instruction set in a computer processor;
translating the first complete instruction set into a second complete instruction set; and
executing a process on the computer processor using only the second complete instruction set.
13 . The process of claim 12 , wherein the first complete instruction set is native to the computer processor; and wherein the second complete instruction set is not native to the computer processor.
14 . The process of claim 12 , comprising translating the first complete instruction set into the second complete instruction at boot up of the computer processor.
15 . The process of claim 12 , comprising translating the first complete instruction set into the second complete instruction set in connection with loading program code for a process that is executed by the computer processor;
wherein the process executes using the second complete instruction set; and
wherein other processes in the computer processor execute using the first complete instruction set.
16 . The process of claim 12 , comprising mapping each instruction in the first complete instruction set to a corresponding instruction of substantially equivalent function in the second complete instructions set;
wherein the byte code for each instruction in the first complete instruction set is different than the byte code for the corresponding instruction of substantially equivalent function in the second complete instruction set.
17 . The process of claim 12 , comprising:
generating a randomized second complete instruction set; and
using a translation seed to generate the randomized second complete instruction set; and
storing the translation seed in a secure location in a kernel of an operating system.
18 . The process of claim 12 , comprising transferring a process and a translate table associated with the process or a translation seed associated with the process to a second computer processor.
19 . The process of claim 12 , comprising generating a globally unique second complete instruction set in relation to one or more of a particular computer processor, a particular instantiation of an operating system, a particular process executing in the computer processor, and a particular thread associated with the particular process.
20 . A computer readable storage device comprising instructions that when executed by a processor execute a process comprising:
maintaining a first complete instruction set in a computer processor;
translating the first complete instruction set into a second complete instruction set; and
executing a process on the computer processor using only the second complete instruction set.