Majority determination circuit, majority determination method, and semiconductor device

1. A majority determination circuit comprising:

a first determination unit suitable for determining a first majority between bits of a first logic value and a second logic value in a first odd-bit data, wherein the first odd-bit data is an even-bit data with absence of a first bit;

a second determination unit suitable for determining a second majority between bits of the first logic value and the second logic value in a second odd-bit data, wherein the second odd-bit data is the even-bit data with absence of a second bit;

and a result combination unit suitable for determining a third majority between bits of the first logic value and the second logic value in the even-bit data based on the first majority and the second majority.

2. The circuit of claim 1 , wherein the first determination unit determines the first majority in response to the first odd-bit data and inverted first odd-bit data, and

wherein the second determination unit determines the second majority in response to the second odd-bit data and inverted second odd-bit data.

3. The circuit of claim 1 , wherein the result combination unit determines that the first logic value is the third majority when the first majority and the second majority indicate the first logic value, and determines that the second logic value is the third majority when the first majority and the second majority indicate the second logic value.

4. The circuit of claim 3 , wherein each of the first determination unit and the second determination unit outputs the first logic value when the first majority and the second majority indicate the first logic value, and outputs the second logic value when the first majority and the second majority indicate the second logic value, and

wherein the result combination unit outputs preset one from the first and second logic values when the first majority and the second majority are different from each other.

5. The circuit of claim 2 , wherein current flowing through the first determination unit depends on a value of the first odd-bit data, and current flowing through the second determination unit depends on a value of the second odd-bit data.

6. The circuit of claim 5 , wherein the first determination unit comprises:

a first current sourcing unit for sourcing a current flowing through a first node in response to a voltage of the first node;

a second current sourcing unit for sourcing a current flowing through a second node in response to the voltage of the first node;

a first current sinking unit for sinking the current flowing through the first node by an amount determined by the value of the first odd-bit data; and

a second current sinking unit for sinking the current flowing through the second node by an amount determined by a value of the inverted first odd-bit data, and

wherein the first majority corresponds to a voltage of the second node.

7. The circuit of claim 6 , wherein the first current sourcing unit comprises a first transistor configured to be coupled between the first node and a power supply voltage and to be controlled by the voltage of the first node,

the second current sourcing unit comprises a second transistor configured to be coupled between the second node and the power supply voltage and to be controlled by the voltage of the first node,

the first current sinking unit comprises one or more third transistors configured to be coupled between the first node and a first common node and to be controlled by values of corresponding bits of the first odd-bit data, and

the second current sinking unit comprises one or more fourth transistors configured to be coupled between the second node and the first common node and to be controlled by values of corresponding bits of the inverted first odd-bit data.

8. The circuit of claim 7 , wherein the second determination unit comprises:

a third current sourcing unit for sourcing a current flowing through a third node in response to a voltage of the third node;

a fourth current sourcing unit for sourcing a current flowing through a fourth node in response to the voltage of the third node;

a third current sinking unit for sinking the current flowing through the third node by an amount determined by the value of the second odd-bit data; and

a fourth current sinking unit for sinking the current flowing through the fourth node by an amount determined by a value of the inverted second odd-bit data, and

wherein the second majority corresponds to a voltage of the fourth node.

9. The circuit of claim 8 , wherein the third current sourcing unit comprises a fifth transistor configured to be coupled between the third node and the power supply voltage and to be controlled by the voltage of the third node,

the fourth current sourcing unit comprises a sixth transistor configured to be coupled between the fourth node and the power supply voltage and to be controlled by the voltage of the third node;

the third current sinking unit comprises one or more seventh transistors configured to be coupled between the third node and a second common node and to be controlled by values of corresponding bits of the second odd-bit data; and

the fourth current sinking unit comprises one or more eighth transistors configured to be coupled between the fourth node and the second common node and to be controlled by values of corresponding bits of the inverted second odd-bit data.

10. The circuit of claim 9 , wherein the result combination unit comprises a logic gate for outputting a combination of the first majority and the second majority, wherein the combination corresponding to a determination result of the result combination unit.

11. A majority determination method comprising:

determining a first majority between bits of a first logic value and a second logic value in a first odd-bit data, wherein the first odd-bit data is an even-bit data with absence of a first bit;

determining a second majority between bits of the first logic value and the second logic value in a second odd-bit data, wherein the second odd-bit data is the even-bit data with absence of a second bit;

and determining a third majority between bits of the first logic value and the second logic value in the even-bit data based on the first majority and the second majority.

12. The method of claim 11 , wherein determining the first majority determines the first majority in response to the first odd-bit data and inverted first odd-bit data, and

wherein determining the second majority determines the second majority in response to the second odd-bit data and inverted second odd-bit data.

13. The method of claim 11 , wherein determining the third majority determines that the first logic value is the third majority when the first majority and the second majority indicate the first logic value and determines that the second logic value is the third majority when the first majority and the second majority indicate the second logic value.

14. The method of claim 13 , wherein each of determining the first majority and determining the second majority outputs the first logic value when the first majority and the second majority indicate the first logic value and outputs the second logic value when the first majority and the second majority indicate the second logic value, and

wherein determining the third majority outputs preset one from the first and second logic values when the first majority and the second majority are different to each other.

15. A semiconductor device comprising:

a plurality of first data lines;

a plurality of second data lines;

a majority determination unit suitable for combining a first majority between bits of a first logic value and a second logic value in a first odd-bit data with a second majority between bits of the first logic value and the second logic value in a second odd-bit data and for determining a third majority between bits of the first logic value and the second logic value in an even-bit data based on the first majority and the second majority; and

a data transmission unit suitable for transmitting the even-bit data transmitted through the plurality of first data lines to the plurality of second data lines after selectively inverting the even-bit data based on the third majority,

wherein the first odd-bit data is the even-bit data with absence of the first bit, and the second odd-bit data is the even-bit data with absence of the second bit.

16. The device of claim 15 , wherein the data transmission unit delays the even-bit data until the majority determination unit to determine the third majority.

17. The device of claim 16 , wherein the majority determination unit comprises:

a first determination unit for determining the first majority;

a second determination unit for determining the second majority; and

a result combination unit for determining the third majority.

18. The device of claim 16 , wherein the data transmission unit comprises:

a delay unit for delaying the even-bit data until the majority determination unit to determine the third majority; and

a selection unit for selecting one from an output and an inverted output of the delay unit in response to the third majority and transmitting an output of the selection unit to the plurality of second data lines.